Force SPARC/CPCI-520G, Техническое справочное руководство

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Processor – UltraSPARC-IIi Hardware Description
Page 74 SPARC/CPCI-52x(G)
6.1.5 UltraSPARC-IIi PCI Bus Interface
The CPU uses a 66 MHz PCI bus as its bus for I/O extensions. This bus is
32 bits wide.
For a list of devices connected to the UltraSPARC-IIi PCI bus, see
table 28 “Buses, bus modes, and connected devices” on page 67.
Table 35 UltraSPARC-IIi PCI address space (8 GByte)
Address range in
PA<40:0>
Size Description Generated PCI commands
1FE.0000.0000
16
…1FE.00FF.FFFF
16
16 MByte CPU internal CSR space n.a.
1FE.0100.0000
16
…1FE.01FF.FFFF
16
16 MByte PCI configuration space Configuration read or write
(may be special cycle)
1FE.0200.0000
16
…1FE.02FF.FFFF
16
16 MByte PCI bus I/O space I/O read or write
1FE.0300.0000
16
…1FE.FFFF.FFFF
16
4 GByte
minus
48 MByte reserved reserved
1FF.0000.0000
16
…1FF.FFFF.FFFF
16
4 GByte PCI bus memory space Memory read or write