Force SPARC/CPCI-520G, Техническое справочное руководство

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Ethernet and EBus2 Devices – PCIO Hardware Description
Page 94 SPARC/CPCI-52x(G)
6.3.12 SCR: ENUM Interrupt
Note: All SPARC/CPCI-52x(G) variants provide the ENUM #1
interrupt since this is the ENUM interrupt of the CompactPCI
interface related to the base board of the SPARC/CPCI-52x(G).
However, note that in case of using the I/O-523G and only in this
case, there is a second ENUM interrupt related to the CompactPCI
interface of the I/O board: ENUM #2. ENUM #1 and ENUM #2
utilize the same interrupt request pin. Therefore the interrupt
handler must determine the actual interrupt source by reading
IP_ENUM1
and
IP_ENUM2
.
IE_ENUM x
(r/w)
IE_ENUM x
specifies if the respective ENUM #x interrupt is enabled
(x=1 or 2). Only if enabled an interrupt is generated to the processor in
case of a pending ENUM interrupt.
= 0
(default) ENUM #x interrupt is disabled.
= 1
ENUM #x interrupt is enabled.
IP_ENUM x
(r/w)
IP_ENUM x
indicates the status of the ENUM #x signal on the respective
CompactPCI interface
• on the base board’s CompactPCI interface in case of
IP_ENUM1
• or on the I/O-523G CompactPCI interface in case of
IP_ENUM2
.
= 0
The respective ENUM signal is high that is it is inactive.
= 1
The respective ENUM signal is low that is it is active.
Table 53 ENUM Interrupt Control Register
F160.000A
16
Bit 7 6 5 4 3 2 1 0
Value
1 1 1 1 IP_
ENUM2
IE_
ENUM2
IP_
ENUM1
IE_
ENUM1