Force SPARC/CPCI-520G, Техническое справочное руководство

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Hardware Description Ethernet and EBus2 Devices – PCIO
SPARC/CPCI-52x(G) Page 81
• Protocol support (HDLC/SDLC)
• Interrupt controlled
6.3.5 Keyboard/Mouse, FDC and Parallel Interface – Super I/O
To implement a major part of the UltraSPARC-IIi architecture’s I/O-sub-
system a standard PC Super I/O device is utilized, the Super I/O –
PC87332VLJ at PCI bus base address
F130.000016
on the EBus2.
Device features The Super I/O is a single chip solution for most commonly used I/O pe-
ripherals in ISA based computers. It incorporates
• a floppy disk controller (FDC, see “Floppy interface” on page 81),
• 2 UARTs which are fully NS16450 and NS16550 compatible and
which are used for the SUN style keyboard/mouse interface,
• and an IEEE1284 compatible parallel interface with EPP (Enhanced
Parallel Port) and ECP (Enhanced Capabilities Port) compatibility
(see “Parallel interface” on page 82).
Standard PC-AT address decoding for all the on-chip peripherals and a
set of configuration registers are also implemented together with ad-
vanced power management features.
Floppy interface The floppy disk controller uses a high performance digital data separator,
eliminating the need for any external filter components. One of the 4
DMA channels of the PCIO EBus2 is used for the Super-I/O floppy inter-
face (see table 38 “PCIO EBus2 DMA channels” on page 78).
• Software compatible with the PC8477
• Superset of DP8473, the 765A and the N82077
• 16-byte FIFO (disabled by default)
• Burst and non-burst modes
• Perpendicular recording drive support
• High-performance internal digital data separator (no external filter
components required)
• Low-power CMOS with enhanced power-down mode
• Automatic media-sense support
• Support of all popular 5.25” and 3.5” floppy drives, including the
2.88 MByte 3.5” floppy drive
• Support of fast 2 Mbps and standard 1 Mbps/500 Kbps/250 Kbps
tape drives