Force SPARC/CPCI-520G, Техническое справочное руководство

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Base-520(G) Installation Front Panel and Connectors
SPARC/CPCI-52x(G) Page 29
Table 12 Front panel features
Device Description
RESET Mechanical reset key:
When enabled and toggled it instantaneously affects
the SPARC/CPCI-52x(G) by generating a push-but-
ton Power On Reset (POR) to the UltraSPARC-IIi.
Push-button Power On Reset has the same effect as a
Power On Reset from the power supply, with the only
difference, that the corresponding status bit (
B_POR
)
in the UltraSPARC-IIi
Reset_Control
Register is
set and the DRAM refresh is not influenced.
For information on disabling the reset key,
see “SW4-1” on page 27.
ABORT Mechanical abort key:
When enabled and toggled it instantaneously affects
the SPARC/CPCI-52x(G) by generating a push-but-
ton external initiated reset (XIR). Push-button exter-
nal initiated reset allows a user-reset (abort) of part of
the processor without resetting the whole system.
UltraSPARC-IIi sets the
B_XIR
bit in the
Reset_Control Register when a push-button ex-
ternal initiated reset is detected.
For information on disabling the abort key, see
“SW4-2” on page 27.
DIAG Software programmable hexadecimal display for di-
agnostics.
MODE Hexadecimal rotary switch, decoded with 4 bit. De-
fault setting: F
16
.
RUN CPU status LED:
green
normal operation
red
the processor is halted or reset is active;
it starts blinking to signal that the processor did not
access the PCI bus for more than 1 second.
BM CompactPCI busmaster LED:
green
if the SPARC/CPCI-52x(G) accesses the Compact-
PCI as master
off
otherwise