Force SPARC/CPCI-520G, Техническое справочное руководство

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Ethernet and EBus2 Devices – PCIO Hardware Description
Page 76 SPARC/CPCI-52x(G)
• Expansion bus 2 interface (EBus2), supporting up to 8 external
devices and 4 buffered slave DMA channels.
6.3.1 Ethernet Interface – PCIO
The PCIO on the Base-520(G) delivers the Ethernet #1 interface and the
PCIO on the I/O-52x(G) delivers the Ethernet #2 interface. As described
above, the PCIO provides Ethernet via a media independent interface
(MII). An additional on-board PHYceiver transforms the MII into a
10/100-BaseT interface.
The Ethernet interface consists of 2 major function blocks:
• High performance two-channel DVMA host interface between the
MAC and the PCI bus with interrupt generation capability
• Media Access Control (MAC) function for a 10/100 Mbit/s
CSMA/CD protocol based network compatible with IEEE 802.3/Eth-
ernet
DVMA The PCIO DVMA controller enables the Ethernet interface to transfer
data to and from the main memory. PCIO supports full duplex operation
and provides 2 KByte local on-chip buffers (FIFOs) in each direction.
On-board
PHYceiver The Twisted Pair Ethernet interface is realized via a PHYceiver device,
the PHYceiver - ICS1890. It is directly connected to the MII interface of
the PCIO. The PHYceiver is a fully integrated physical layer device sup-
porting 10 and 100 Mbit/s CSMA/CD Ethernet applications. The PHY-
ceiver is compliant with ISO/IEC 8802-3 Ethernet standard for 10- and
100-Mbit/s operation. A station management interface (MII management
interface) is provided to enable command and status information ex-
change between PCIO and PHYceiver. The PHYceiver supports shielded
twisted pair (STP) and unshielded twisted pair (UTP) category 5 cables
up to 105 m. Operation in half duplex or full duplex mode at either 10 or
100 Mbit/s is possible with control by auto-negotiation or manual selec-
tion. By employing auto-negotiation the technology capabilities of the re-
mote link partner may be determined and operation automatically
adjusted to the highest performance operating mode common to both.
The on-board PHYceiver address is hardwired to
01
16
as defined by the
MII management interface IEEE specification.
Ethernet
interrupt The Ethernet controller uses the Ethernet interrupt on the UIC for inter-
rupting the UltraSPARC-IIi (see table 33 “Interrupt sources from the
Base-520(G)” on page 72 and table 34 “Interrupt sources from the
I/O-52x(G)” on page 73).