Force SPARC/CPCI-520G, Техническое справочное руководство

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Processor – UltraSPARC-IIi Hardware Description
Page 72 SPARC/CPCI-52x(G)
6.1.4 Interrupt Map
Interrupt concept The UltraSPARC-IIi provides a 6-bit wide interrupt vector for 63 inter-
rupt sources. A separate device, the UPA interrupt concentrator (UIC),
provides the inputs for all necessary interrupts. The UIC monitors all in-
terrupts by a round-robin-scheme with 33 MHz, converts them to an own
vector and transmits this vector to the processor. The processor interrupt
PCI unit (PIE) reflects every vector in 1 state bit. From the state bit a new
vector is generated and transmitted to the processor’s execution unit. If
more than 1 interrupt state bit is active, the transmitting sequence of the
new interrupt vector is priority controlled.
Enabling
interrupts Every interrupt routed to the UIC can be separately enabled or disabled in
the interrupt source and in the processor.
The following table lists all interrupt sources, their vectors from the UIC
to the PIE, their vectors from the PIE to the processor’s execution unit
and the respective priority.
Table 33 Interrupt sources from the Base-520(G)
Function Device
UIC
vector CPU internal
vector CPU internal
priority
Ethernet #1 PCIO
21
16
21
16
3
SCSI #1 SYM53C875
20
16
20
16
3
Serial SAB82532
2d
16
2b
16
7
Keyboard Super I/O
2b
16
29
16
4
Mouse
2c
16
2a
16
4
Floppy
29
16
27
16
8
Parallel
22
16
22
16
2
UPA64 S UPA64S card
23
16
software controlled 5
Audio playback CS4231
1f
16
24
16
7
Audio capture
24
16
23
16
8
WatchDog EBus2 CTRL
18
16
0c
16
6
Temperature
02
16
03
16
2
ENUM
1a
16
0f
16
1
CompactPCI #A CompactPCI
0f
16
04
16
7
CompactPCI #B
0d
16
05
16
5
CompactPCI #C
1d
16
06
16
5
CompactPCI #D
0a
16
07
16
2