Force SPARC/CPCI-520G, Техническое справочное руководство

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Hardware Description
SPARC/CPCI-52x(G) Page 67
The following table gives an overview of the different buses, their bus
modes, and the connected devices.
Table 28 Buses, bus modes, and connected devices
Bus and
bus mode
Connected Devices
EC bus,
big endian • UltraSPARC-IIi (see page 68)
• L2 cache with tag (see page 70)
Memory bus,
big endian • UltraSPARC-IIi (see page 68)
• Memory banks (see page 70)
UPA bus,
big endian • UltraSPARC-IIi (see page 68)
• UPA64S card
PCI bus,
little endian • UltraSPARC-IIi (see page 68)
• APB on Base-520(G) and on I/O-52x(G) (see page 75)
PCI A bus on
Base-520(G),
little endian • APB (see page 75)
• CompactPCI interface (see page 75)
PCI bus B on
Base-520(G),
little endian • APB (see page 75)
• Ethernet controller with EBus2 interface (PCIO) (see page 75)
• SCSI controller (see page 97)
EBus2,
little endian • Serial I/O interfaces (see page 80)
• Keyboard/Mouse, parallel and floppy interface (see page 81)
• Audio interface (see page 84)
• RTC/NVRAM (see page 83)
• Boot PROM, boot and user flash EPROM (see page 79)
• System Configuration Registers (see page 85)
PCI bus A on
I/O-52x(G),
little endian • APB (see page 75)
• only I/O-523G: CompactPCI interface (see page 75)
PCI bus B on
I/O-52x(G),
little endian • APB (see page 75)
• Ethernet controller (PCIO) (see page 75)
• SCSI controller (see page 97)
• 2 PMC modules (see page 98)