Force SPARC/CPCI-520G, Техническое справочное руководство

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Hardware Description APB (Advanced PCI Bridge) and CompactPCI Interface
SPARC/CPCI-52x(G) Page 75
6.2 APB (Advanced PCI Bridge) and CompactPCI Interface
The APB (Advance PCI Bridge) is a PCI-to-dual-PCI bus bridge and is
assembled on the base and on the I/O board (see figure 23 “Block Dia-
gram of the SPARC/CPCI-52x(G)” on page 66). Both drive 2 secondary
PCI buses A and B.
• The Base-520(G) APB supports the CompactPCI interface #1 on PCI
bus A and the local PCI interface on PCI bus B. On PCI bus B there
are additional local PCI devices providing:
– SCSI #1 (see section 6.4 “SCSI Interface – SYM53C875” on
page 97),
– as well as Ethernet #1 and access to interfaces implemented by
EBus2 devices (see section 6.3 “Ethernet and EBus2 Devices –
PCIO” on page 75).
• The I/O-523G APB supports the CompactPCI interface #2 on PCI
bus A. On the I/O-522(G) this bus is not used. On PCI bus B there are
additional local PCI devices in both cases providing:
– 2 PMC Slots with Busmode Support (see page 98),
– SCSI #2 (see section 6.4 “SCSI Interface – SYM53C875” on
page 97),
– and Ethernet #2 (see section 6.3 “Ethernet and EBus2 Devices –
PCIO” on page 75).
T
he backplane
CompactPCI
bus is connected via the
PCI bus A
of
the APBs.
A separate arbiter is used to support up to 7 CompactPCI I/O
devices. A separate PLL is used to deliver 7 individual clocks for the
CompactPCI I/O devices.
6.3 Ethernet and EBus2 Devices – PCIO
PCIO features PCIO is a high integration, high performance single chip IO subsystem
using a single PCI bus load. As a dual PCI device, PCIO delivers Ether-
net and EBus2 functionality to the SPARC/CPCI-52x(G) (see
section 6.3.1 “Ethernet Interface – PCIO” on page 76 and section 6.3.2
“EBus2 Interface – PCIO” on page 77).
• PCI Local Bus specification 2.1 compliant master/slave interface
• 10/100BaseT Ethernet using a derivative of Media Access Control
(MAC), with fully buffered transmit and receive channels; media
independent interface (MII)