Force SPARC/CPCI-520G, Техническое справочное руководство

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Processor – UltraSPARC-IIi Hardware Description
Page 70 SPARC/CPCI-52x(G)
6.1.2 External Cache Control Unit
The UltraSPARC-IIi obtains an integrated L2 cache controller providing
a backside interface with a 72-bit wide data bus and 150 MHz speed. The
L2 cache capacity is either 256 KByte or 1 MByte. 3 synchronous late
write SRAM devices (2 for data and 1 for the tags) are provided.
6.1.3 Memory Controller Unit, Memory Modules, and Main Memory Configuration
Memory
controller unit The memory controller unit of the SPARC/CPCI-52x(G) is included in
the UltraSPARC-IIi. The memory interface provides full EDO DRAM
support including refresh. It uses 8 RAS lines to select 8 DRAM banks
and 2 identical CAS signals. The memory interface is 72 bit wide, 64 bits
are shared with the UPA64S interface and 8 bits are used for ECC. 6 bidi-
rectional registered multiplexers and demultiplexers (XCVRs) are used to
extend the memory interface from 72 bit to 144 bit. The control of the
XCVRs is also included in the UltraSPARC-IIi. 60 ns EDO DRAMs with
10-bit column address (CAS) are supported.
The CPU supports the following accesses to main memory:
• Refresh: Refresh is a 4-way staggered CAS before RAS refresh. One
refresh at a time refreshes the 2 memory banks of 1 memory module.
• 64-byte read to fill one L2 cache line: containing 1 burst access (EDO
fast page mode) with 4 data (CAS) cycles each 128 bit wide
(16 byte).
• 64-byte write to flush one L2 cache line: containing 1 burst access
(EDO fast page mode) with 4 data (CAS) cycles each 128 bit wide
(16 byte). To write data words smaller than 64 byte,
– fill 1 cache line,
– modify this cache line,
– and write it back.