Force SPARC/CPCI-520G, Техническое справочное руководство

Страница: 99 / 134

Hardware Description Ethernet and EBus2 Devices – PCIO
SPARC/CPCI-52x(G) Page 85
6.3.8 System Configuration Registers – SCR
The Base-520(G) implements a set of system configuration registers via a
field programmable gate array XC4003E (FPGA Xilinx LCA) at PCI bus
base address
F160.000016
on the EBus2. The table below gives an
overview of all SPARC/CPCI-52x(G) system configuration registers:
Table 41 System configuration register set (SCR), all 8-bit wide
PCI bus addr.
Reset
value
Description
F160.000016
(LED 1) and
F160.000116
(LED 2)
F0
16
User LED x Control Registers, x = 1, 2 (see page 86)
F160.000216 F3
16
Boot and User Flash Size Control Register (see page 90)
F160.000316 F0
16
I2C Bus Control and Status Register (see page 96)
F160.000416 F0
16
Miscellaneous Control Register (see page 93)
F160.000516 F0
16
Miscellaneous Control and Status Register (see page 91)
F160.000616 F0
16
Watchdog and Temperature Control and Status Register (see
page 91)
F160.000716 F0
16
Watchdog Timer Trigger Register (see page 91)
F160.0008
16
F0
16
reserved
F160.0009
16
F160.000A16 F0
16
ENUM Interrupt Control Register (see page 94)
F160.000B
16
FF
16
reserved
F160.000C
16
F160.000D
16
F160.000E16 FX
16
Reset Status Register (see page 92)
F160.000F16 FX
16
System Configuration Identification Register (see page 86)
F160.001016 00
16
7-Segment LED Display Control Register (see page 87)
F160.001116 XX
16
Rotary Switch Status Register (see page 87)
F160.001216 XX
16
SW4 and SW5 Status Register (see page 89)
F160.0013
16
XF
16
reserved