Force SPARC/CPCI-520G, Техническое справочное руководство, Страница: 103 / 134

Hardware Description Ethernet and EBus2 Devices – PCIO
SPARC/CPCI-52x(G) Page 89
SWx-y (ro),
except
SW5-2
SWx-y indicates the setting of the respective switch (see table 11 “De-
fault switch settings” on page 27):
• SW5-4 – Reserved, must be OFF (see page 28)
• SW6-2 – Boot device selection (OFF = boot from boot PROM, see
page 28)
• SW5-3 – Reserved, must be OFF (see page 28)
• SW5-1 – SCSI Termination for SCSI #1 on front panel (OFF = front
panel termination automatic, see page 28)
• SW4-4 – User flash EPROM write protection (OFF = user flash
EPROM write protected, see page 27)
• SW4-3 – Boot flash EPROM write protection (OFF = boot flash
EPROM write protected, see page 27)
= 0
Switch is ON.
= 1
Switch is OFF.
SW5-2 (ro) SW5-2 indicates the setting of the SW5-2: SCSI Termination for SCSI
#1 on P2 (OFF = backplane termination disabled, see page 28).
= 0 Switch is OFF.
= 1
Switch is ON.
6.3.10 SCR: Boot and User Flash
The Boot and User Flash Size Control Register within the system config-
uration register set indicates the decoding of
EBus_CS#0
according to
the assembled flash device type (see section 6.3.3 “Boot PROM, Boot
and User Flash EPROM” on page 79).
Note: OpenBoot initializes the Boot and User Flash Size Control
Register during power up with the correct value. Note also that
BOOTROM_SIZE only concerns the boot flash EPROM, whereas the
boot PROM is always decoded to 1 MByte. Therefore never
reprogram this register.
Table 46 SW4 and SW5 Status Register
F160.0012
16
Bit 7 6 5 4 3 2 1 0
Value 1 SW5-4 SW6-2 SW5-3 SW5-2 SW5-1 SW4-4 SW4-3