Force SPARC/CPCI-520G, Техническое справочное руководство

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Ethernet and EBus2 Devices – PCIO Hardware Description
Page 92 SPARC/CPCI-52x(G)
IP_TEMP
(ro)
IP_TEMP
indicates whether one of the 2 temperature sensors signals an
alarm condition. Only if enabled via appropriate setting of
IE_TEMP
, an
interrupt is generated.
= 0
No temperature control interrupt is pending.
= 1
A temperature control interrupt is pending.
IE_TEMP
(r/w)
IE_TEMP
specifies whether the generation of temperature control inter-
rupts is enabled or disabled. A pending temperature control interrupt is
indicated by
IP_TEMP
.
= 0
Interrupt generation disabled (default after reset).
= 1
Interrupt generation enabled.
IE_WDT
(r/w)
IE_WDT
specifies whether the generation of watchdog timer interrupts is
enabled or disabled. A pending watchdog timer interrupt is indicated by
WDT_RESET
in the Reset Status Register.
= 0 Interrupt generation disabled (default after reset).
= 1
Interrupt generation enabled.
IS_WDT
(ro)
IS_WDT
indicates status of the
WDO
output signal and thereby indicates
the status of the watchdog timer if started (see “Watchdog” on page 90).
= 0
Watchdog timeout.
= 1 Watchdog timer has not expired.
The Reset Status Register allows to identify the on-board reset source
which generated the latest hardware reset:
• watchdog – WDT_RESET ,
• CompactPCI reset – BUS_RESET ,
• front-panel reset key –
KEY_RESET
,
• or power-on reset: If all status bits in the Reset Status Register are
cleared (0) after a reset, the reset has been generated due to a power-
on reset. A power-on reset occurs when the power supply unit is
turned on, or the power supply sensor detects that one of the required
power supply voltages falls below a tolerable limit.
Table 51 Reset Status Register
F160.000E
16
Bit 7 6 5 4 3 2 1 0
Value
1 1 1 1 1 WDT_
RESET
BUS_
RESET
KEY_
RESET