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Validity of the inputs (”RD” register)
This 16 bit word shows faults which arise on
updating the RIW images of the inputs to the
valve terminal. The high byte of RD is produ-
ced by the valve terminal, the low byte by the
PLC.
For the high byte from the valve terminal:
•
RD (Highbyte) = 0:
Values of the valve terminal inputs are valid
and can be processed by the control pro-
gram.
•
RD (Highbyte) < > 0:
V
SEN
error in the valve terminal, input value
invalid.
The low byte of RD is produced by the PLC
CPU. It relates to the cyclic updating of the
inputs through the FIPIO bus. If it is not zero,
the RIW variables representing the image of the
inputs might contain old and inaccurate data
and must therefore be ignored by the program.
The RD register and the RIW words (image of
the inputs) will not be updated, as long as the
PLC is in the STOP condition - they retain their
last values.
VIFB16 - 03/05 5. Diagnosis/error treatment
5-18
0506b