ETOP P/I-P3BVL, Руководство пользователя

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Chapter 3 BIOS Configuration
46 P/I-P3BVL User's Manual
SDRAM CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles of
CAS latency depends on the DRAM timing. Do not reset this field
from the default value specified by the system designer. The default
setting is
3
.
DRAM Data Integrity Mode
This option sets the data integrity mode of the DRAM installed in the
system. The default setting is
Non-ECC
.
System BIOS Cacheable
When enabled, access to the system BIOS ROM addressed at
F0000H-FFFFFH are cached, provided that the cache controller is
disabled.
Video BIOS Cacheable
When enabled, access to video BIOS addressed at C0000H to C7FFFH
are cached, provided that the cache controller is disabled.
Video RAM Cacheable
Selecting
Enabled
allows caching of the video BIOS ROM at C0000h
to C7FFFh, resulting in better video performance. However, if any
program writes to this memory area, a memory access error may result.
8 Bit I/O Recovery Time
This option specifies the length of the delay (in sysclks) inserted
between consecutive 8-bit I/O operations. The settings are 1, 2, 3, 4, 5,
6, 7, or 8. The default setting is
3
.
16 Bit I/O Recovery Time
This option specifies the length of the delay (in sysclks) inserted
between consecutive 16-bit I/O operations. The settings are 1, 2, 3, 4, 5,
6, 7, or 8. The default setting is
2
.
Memory Hole at 15MB - 16MB
In order to improve performance, certain space in memory can be
reserved for ISA cards. This field allows you to reserve 15MB to
16MB memory address space to ISA expansion cards. This makes
memory from 15MB and up unavailable to the system. Expansion cards
can only access memory up to 16MB. The default of this field is set to
Disabled
.