F800 CIRCUIT DESCRIPTION
7 (25)
Uppgjord (även faktaansvarig om annan) -
Prepared (also subject responsible if other)
Nr
-
No.
KL/ECS/S/LT Magnus Lindahl
ECS/S/LT-96:5044
Dokansv/Godk -
Doc respons/Approved
Kontr
-
Checked
Datum
-
Date
Rev
File
KI/ECS/S/LTC
1996-06-06
A
965044.DOC
Reference oscillator
The common reference oscillator is a crystal controlled oscillator with fixed frequency.
In F800 versions made for 25 kHz channel spacing the reference frequency used is 9
MHz.
The crystal oscillator obtains bias voltage from the PLL circuit. The signal from the
reference oscillator is fed to the PLL circuit where it is divided by a internal divider to
create the internal PLL reference. The internal PLL reference signal is 12,5 kHz in all
versions that works with 25 kHz channel spacing.
In duplex versions the same reference oscillator is used for the RCS frequency
generator as well as the TX frequency generator.
PLL circuit and loop filter
The PLL circuit controls the VCO. The VCO signal is compared with the reference
signal in the PLL circuit. The phases of the two signals are compared. Since the
frequencies of the two signals are not at all the same, 9 MHz from the reference
oscillator and the VCO signal have at least 10 times higher frequency, the signals
must be divided down to a common frequency.
The PLL circuit has three internal programmable divider stages, one for the reference
signal and two for the VCO signal. The denominators, i.e. the contents of the divider
stages, are loaded into the PLL circuit by data from the CPU- board. According to the
loaded denominators, the PLL circuit will activate a signal for control of the external
prescaler.
The prescaler denominator has two fixed values, 40 or 41 for F802 and F804 and 64
or 65 for F805. Selection of one of the two denominator values is done through the
PLL circuit.
The data for the PLL circuit is loaded as eight nibbles of four bits, two nibbles for
each of the divider used to divide the VCO signal and one nibble for the divider used
for the reference oscillator signal. In the remaining nibble there is also information
used for control of the prescaler. The serial data is clocked into the registers ( dividers
) of the PLL circuit by a clock signal. The registers in the PLL circuit are made
accessible by a strobe signal. In the case there are two PLL circuits for duplex
operation each PLL circuit has it’s own strobe signal but the clock and data signals are
common. The three least significant bits of the address bus from the CPU- board are
used for addressing the different registers in the PLL circuit. The data is obtained
through the four least significant bits of the databus from the CPU- board.
