F800 CIRCUIT DESCRIPTION
23 (25)
Uppgjord (även faktaansvarig om annan) -
Prepared (also subject responsible if other)
Nr
-
No.
KL/ECS/S/LT Magnus Lindahl
ECS/S/LT-96:5044
Dokansv/Godk -
Doc respons/Approved
Kontr
-
Checked
Datum
-
Date
Rev
File
KI/ECS/S/LTC
1996-06-06
A
965044.DOC
Tuning of RX front end
The tuning of the RF front end depends on which frequency the receiver is active on.
The tuning is controlled by a voltage that is connected to capacitance-diodes in the
front end. The voltage is generated on the radio board and connected to a variable
resistance on the processor board. The resistance is controlled in 16 steps from the
processor via an outport. The voltage divider is formed by the switches in Z24 and
R57-R61.
From outport
+12V
Radio board
FIG P: Block diagram tuning of RF front end
Channel selection
A channel is chosen by loading channel information into the PLL circuit in the
synthesiser on the radio board.
The channel information consists of a PLL address, a divider and band selection. The
PLL address is used for selection of RX-synthesiser or TX-synthesiser in a duplex
station. The divider is loaded into the PLL circuit as a 4-bit word. The choice of which
band the VCO shall use is made by the band selection.
The channel information is generated by the program and fed to the processor
controlled outports, Z13/V6-V9 and Z15.
