F800 CIRCUIT DESCRIPTION
20 (25)
Uppgjord (även faktaansvarig om annan) -
Prepared (also subject responsible if other)
Nr
-
No.
KL/ECS/S/LT Magnus Lindahl
ECS/S/LT-96:5044
Dokansv/Godk -
Doc respons/Approved
Kontr
-
Checked
Datum
-
Date
Rev
File
KI/ECS/S/LTC
1996-06-06
A
965044.DOC
The V20 is a CMOS 16- bit microprocessor with internal 16- bit architecture and an 8-
bit external data-bus. The processor can address 1 Mbytes of memory. The address-
bus is 16 + 4 bits, where the lower 8- bits are multiplexed on the data-bus. There are
4- bits that can be used as the most significant bits of the address-buss or as status
indicators. The 4- bits are used in this application as part of the address-bus, for
memory mapping and for addressing of peripheral circuits. The 4- bits are clocked into
a memory mapping circuit formed by, Z5-Z8, by a control signal from the processor.
The control signal, IO/M, decides if the present information on the address-bus is a
memory or I/O address. Simultaneously as the 8 lower address-bits are present on the
data-buss, the processor generates a strobe signal, QS0. An external address
decoder, latch, Z5; is clocked with the strobe signal and the contents on the data-bus
are stored in the latch. The information from the 8 higher bits of the address-bus, A15
- A8, and the information on the output of the latch, A7 - A0, together form the 16- bit
address-bus. The information on the latch output will remain until a new strobe signal
has been generated by the processor.
The memory, < 1 Mbytes, is located on the processor board. Three different kinds of
memory circuits are used. The software for the F800 is stored in an EPROM, Z2,, the
customer-specific information is stored in an EEPROM, Z4, and temporary information
is stored in a RAM, Z3. Each physical memory position has it’s own address area and
a specific memory enable signal. The memory enable signal is generated by the
memory mapping circuits described earlier.
The processor also has two interrupt inputs, one software maskable and one none
maskable. The interrupt inputs are not used in this application.
On the CPU board there are a number of outports for control of audio switches and
other internal switches. In the same manner there are also a number of inputs for
monitoring of internal events such as squelch on/off etc. External outputs such as fan
control via a buffer transistor to one of the internal outports, Z11, Z12. Signals from
external units such as PTT(TX) are connected via buffer to an internal input, Z9. The
ports are addressed by the processor in the same way as memory circuits but with
one difference, which is the status of the IO/M signal.
Incoming speech
Incoming speech denotes the internal handling, on the processor board of speech
signals from the receiver to the line interface.
Z21A
Z21B
Z26A
Z21B
From outport
RX Line
RX Data
Audio
FIG M: Block diagram for RX AF