Eaton XMCSPAN-001, Инструкция по установке и эксплуатации

Страница: 40 / 48

The PCI/PCI-X bus clocks are generated by the Tsi384 internal clock generator. The clock generator uses REFCLK
positive and negative inputs to generate the clock on PCI_CLK0 outputs. The clock frequency is determined
by PCI_PCIXCAP, PCI_M66EN, and PCI_SEL100. The CPLD on the XMCspan automatically drives PCI_SEL100
high if a PCI-X module is plugged, but an assembly option is provided so that a 133 MHz bus can be selected.
The table below lists all the clocks required by the XMCspan, along with their frequency, source, and clock
target device.
Table 4: Clocking Scheme
Device Frequency Clock Source Clock Signal
PMC Site 1 - Tsi384_1 CLK_PCI1
1
PMC Site 2 - Tsi384_2 CLK_PCI2
1
PEX8533 100 MHz ICS9DB108 CLK_PCIE0
Tsi384 Bridge 1 100 MHz ICS9DB108 CLK_PCIE1
XMC Site 1 100 MHz ICS9DB108 CLK_PCIE2
XMCspan connector J4 100 MHz ICS9DB108 CLK_PCIE8
Tsi384 Bridge 2 100 MHz ICS9DB108 CLK_PCIE9
XMC Site 2 100 MHz ICS9DB108 CLK_PCIE10
1 This depends on what module is plugged.
DEBUGGING SUPPORT
The XMCspan has an 8-position DIP switch that is mainly used for factory testing and debugging.
The following table describes the function of each position on the switch.
Function Default Position
Factory use only OFF SW1-1
Factory use only OFF SW1-2
Factory use only OFF SW1-3
Factory use only OFF SW1-4
Factory use only OFF SW1-5
This is used to enable 133 MHz PCI-X mode for the PMC slots. OFF SW1-6
40
| XMCspan Installation and Use | 6806800H03A
Functional Description