Embedded Solutions
Page 16
pmcparttl_DirL
[$0C Direction Register bits 31-0 read – write ]
DATA BIT
DESCRIPTION
31-0
DIR31-0
Figure 7
PMC-PARALLEL-TTL Direction Lower Bit Map
The lower 32 bits of the parallel port direction are controlled with this port. When reset
this port is cleared 0x00000000. All IO are set to read [inputs]. To use one or more of
the IO for outputs; program the corresponding direction bit(s) to ‘1’.
pmcparttl_DirU
[$10 Direction Register bits 63-32 read – write ]
DATA BIT
DESCRIPTION
31-0
DIR63-32
Figure 8
PMC-PARALLEL-TTL Direction Upper Bit Map
The upper 32 bits of the parallel port direction are controlled with this port. When reset
this port is cleared 0x00000000. All IO are set to read [inputs]. To use one or more of
the IO for outputs; program the corresponding direction bit(s) to ‘1’.
Once a Direction bit is set to output the data in the corresponding output holding register
bit is broadcast on that IO line. The data in the holding register will match the data in
the data output register if the master parallel enable bit is set. If initial states are
important you may want to program the initial data and enable it before enabling the
direction bits.
