Dynamic Engineering PMC-PARALLEL-TTL, Руководство пользователя

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Embedded Solutions Page 11
Address Map
Function Offset
// PMC Parallel TTL definitions
#define pmcparttl_BASE 0x0000 // 0 PMC Parallel TTL base control register offset
#define pmcparttl_ID 0x0004 // 1 PMC Parallel TTL ID Register offset
#define pmcparttl_STATUS 0x0008 // 2 PMC Parallel TTL status Register offset
#define pmcparttl_DirL 0x000c // 3 PMC Parallel TTL Direction lower Register offset
#define pmcparttl_DirU 0x0010 // 4 PMC Parallel TTL Direction upper Register offset
#define pmcparttl_DatL 0x0014 // 5 PMC Parallel TTL Data lower Register, line data read
#define pmcparttl_DatU 0x0018 // 6 PMC Parallel TTL Data upper Register, line data read
#define pmcparttl_DatLreg 0x001c // 7 PMC Parallel TTL Data lower Register read-back
#define pmcparttl_DatUreg 0x0020 // 8 PMC Parallel TTL Data upper Register read-back
#define pmcparttl_COSclk 0x0024 // 9 PMC Parallel TTL COS Clock definition Register
//#define spare 0x0028 // 10 PMC Parallel TTL
#define pmcparttl_RisLreg 0x002c // 11 PMC Parallel TTL Rising lower Register
#define pmcparttl_RisUreg 0x0030 // 12 PMC Parallel TTL Rising upper Register
#define pmcparttl_FallLreg 0x0034 // 13 PMC Parallel TTL Falling lower Register
#define pmcparttl_FallUreg 0x0038 // 14 PMC Parallel TTL Falling upper Register
#define pmcparttl_IntRisLreg 0x003c // 15 PMC Parallel TTL Interrupt Enable Rising lower Register
#define pmcparttl_IntRisUreg 0x0040 // 16 PMC Parallel TTL Interrupt Enable Rising upper Register
#define pmcparttl_IntFallLreg 0x0044 // 17 PMC Parallel TTL Interrupt Enable Falling lower Register
#define pmcparttl_IntFallUreg 0x0048 // 18 PMC Parallel TTL Interrupt Enable Falling upper Register
#define pmcparttl_IntRisLstat 0x004c // 19 PMC Par TTL Interrupt Rising LWR Stat Rd, write = clear
#define pmcparttl_IntRisUstat 0x0050 // 20 PMC Par TTL Interrupt Rising UPR Stat Rd, write = clear
#define pmcparttl_IntFallLstat 0x0054 // 21 PMC Par TTL Interrupt Falling LWR Stat Rd, write = clear
#define pmcparttl_IntFallUstat 0x0058 // 22 PMC Par TTL Interrupt Falling UPR Stat Rd, write = clear
Figure 3 PMC-PARALLEL-TTL Internal Address Map
The address map provided is for the local decoding performed within PMC-Parallel-TTL.
The addresses are all offsets from a base address. The carrier board that the PMC is
installed into provides the base address. Dynamic Engineering prefers a long-word
oriented approach because it is more consistent across platforms.
The map is presented with the #define style to allow cutting and pasting into many
compilers “include” files.
The host system will search the PCI bus to find the assets installed during power-on
initialization. The VendorId = 0x10EE and the CardId = 0x2C for the PMC-Parallel-TTL.