Embedded Solutions
Page 19
pmcparttl_COSclk
[$24 COS clock definition port read -write]
DATA BIT
DESCRIPTION
15
Data Out 0 Enable
14-13
CLOCK PRE-SELECTOR
12
CLOCK POST-SELECTOR
11-0
DIVISOR
Figure 13
PMC-PARALLEL-TTL COS Clk Control Bit Map
Data Out 0 Enable when set and the corresponding Direction bit is set will drive the
COS clock out on Data bit 0. An oscilloscope can be used to verify the frequency
setting that is programmed with the COSclk register.
CLOCK PRE-SELECTOR
00
PCI Clock
01
Oscillator
10
External Clock
11
PCI Clock
The clock pre-selector is used to select which reference clock to use with the divisor
hardware (clock source). The base design oscillator rate is 50 MHz. The external
clock can be any TTL level source driven onto the External Clock input line. The clock
should be free running to be used for this purpose.
POST-SELECTOR when '1' sets the output clock to the divided clock, when '0' sets the
output clock to the pre-selector reference value (clock source).
DIVISOR[11-0] are the clock divisor select bits. The clock source is divided by a 12-bit
counter. The output frequency is {reference / [2(n+1)]}, n>1. The counter divides by
N+1 due to counting from 0 to n before rolling over. The output is then divided by 2 to
produce a square wave output.
The desired frequency of 1 MHz. Is achieved by selecting Osc reference, divided clock
and a factor of 50 with the standard 50 MHz oscillator. 2(N+1) = 50 => N = 24. 0x3018
would be the correct value to write to the COSclk.
