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EN5339QI (NETWORK : IC63, IC64, IC65, IC66)
EN5339QI Pin Discriptions
EN5339QI Block Diagram
EN5339QI
Ordering Information
Part Number Package Markings Temp Rating (°C) Package Description
EN5339QI EN5339 -40 to +85 24-pin (4mm x 6mm x 1.1mm) QFN T&R
EVB-EN5339QI EN5339 QFN Evaluation Board
Packing and Marking Information : www.altera.com/support/reliability/packing/rel-packing-and-marking.html
Pin Assignments (Top View)
NC(SW)
NC(SW) NC(SW) NC(SW)
NC(SW)
PGND
PGND
VOUT
VOUT VOUT VOUT PGND PGND
NC
VFB
AGND
AVIN
POK
ENABLE
PVIN PVIN
26
PGND
25
PGND
1
2
3
4
5 6 7 8 9 10 11 12
13
14
15
16
17
18 19 20
21
22 23 24
Keep-Out
Keep-Out
TST2 TST1 TST0
Figure 3: Pin Out Diagram (Top View)
NOTE A
: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage.
However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.
NOTE B : Grey area highlights exposed metal on the bottom of the package that is not to be mechanically or electrically
connected to the PCB. There should be no traces on PCB top layer under these keep out areas.
NOTE C : White ‘dot’ on top left is pin 1 indicator on top of the device package.
Pin Description
PIN NAME FUNCTION
1, 21-24 NC(SW)
NO CONNECT: These pins are internally connected to the common switching node of the
internal MOSFETs. They must be soldered to PCB but not be electrically connected to any
external signal, ground, or voltage. Failure to follow this guideline may result in device
damage.
2-3, 8-9 PGND
Input and output power ground. Connect these pins to the ground electrode of the input and
output filter capacitors. See VOUT, PVIN descriptions and Layout Recommendation for more
details.
4-7 VOUT
Regulated converter output. Connect to the load and place output filter capacitor(s) between
these pins and PGND pins 8 and 9. See layout recommendation for details
10 TST2 Test Pin. For Altera internal use only. Connect to AVIN at all times.
11 TST1 Test Pin. For Altera internal use only. Connect to AVIN at all times.
www.altera.com/enpirion , Page 2
06903 July 9, 2014 Rev D
EN5339QI
Ordering Information
Part Number Package Markings Temp Rating (°C) Package Description
EN5339QI EN5339 -40 to +85 24-pin (4mm x 6mm x 1.1mm) QFN T&R
EVB-EN5339QI EN5339 QFN Evaluation Board
Packing and Marking Information : www.altera.com/support/reliability/packing/rel-packing-and-marking.html
Pin Assignments (Top View)
NC(SW)
NC(SW) NC(SW) NC(SW)
NC(SW)
PGND
PGND
VOUT
VOUT VOUT VOUT PGND PGND
NC
VFB
AGND
AVIN
POK
ENABLE
PVIN PVIN
26
PGND
25
PGND
1
2
3
4
5 6 7 8 9 10 11 12
13
14
15
16
17
18 19 20
21
22 23 24
Keep-Out
Keep-Out
TST2 TST1 TST0
Figure 3: Pin Out Diagram (Top View)
NOTE A : NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage.
However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.
NOTE B : Grey area highlights exposed metal on the bottom of the package that is not to be mechanically or electrically
connected to the PCB. There should be no traces on PCB top layer under these keep out areas.
NOTE C : White ‘dot’ on top left is pin 1 indicator on top of the device package.
Pin Description
PIN NAME FUNCTION
1, 21-24 NC(SW)
NO CONNECT: These pins are internally connected to the common switching node of the
internal MOSFETs. They must be soldered to PCB but not be electrically connected to any
external signal, ground, or voltage. Failure to follow this guideline may result in device
damage.
2-3, 8-9 PGND
Input and output power ground. Connect these pins to the ground electrode of the input and
output filter capacitors. See VOUT, PVIN descriptions and Layout Recommendation for more
details.
4-7 VOUT
Regulated converter output. Connect to the load and place output filter capacitor(s) between
these pins and PGND pins 8 and 9. See layout recommendation for details
10 TST2 Test Pin. For Altera internal use only. Connect to AVIN at all times.
11 TST1 Test Pin. For Altera internal use only. Connect to AVIN at all times.
www.altera.com/enpirion , Page 2
06903 July 9, 2014 Rev D
EN5339QI
PIN NAME FUNCTION
12 TST0 Test Pin. For Altera internal use only. Connect to AVIN at all times.
13 NC
NO CONNECT: This pin must be soldered to PCB but not electrically connected to any other
pin or to any external signal, voltage, or ground. This pin may be connected internally. Failure
to follow this guideline may result in device damage.
14 VFB
This is the external feedback input pin. A resistor divider connects from the output to AGND.
The mid-point of the resistor divider is connected to VFB. A feed-forward capacitor is
required parallel to the upper feedback resistor (R
A
). The output voltage regulation is based
on the VFB node voltage equal to 0.600V.
15 AGND
The quiet ground for the control circuits. Connect to the ground plane with a via right next to
the pin.
16 AVIN
Analog input voltage for the control circuits. Connect this pin to the input power supply (PVIN)
at a quiet point. Decouple with a 1uF capacitor to AGND.
17 POK
POK is an open drain output. Refer to Power OK section for details. Leave POK open if
unused.
18 ENABLE
Output Enable. A logic high level on this pin enables the output and initiates a soft-start. A
logic low signal disables the output and discharges the output to GND. This pin must not be
left floating.
19-20 PVIN
Input power supply. Connect to input power supply and place input filter capacitor(s) between
these pins and PGND pins 2 to 3.
25,26 PGND
Not a perimeter pin. Device thermal pad to be connected to the system GND plane for heat-
sinking purposes. See Layout Recommendation section.
www.altera.com/enpirion , Page 3
06903 July 9, 2014 Rev D
EN5339QI
Functional Block Diagram
DAC
VREF
(+)
(-)
Error
Amp
VFB
VOUT
Package Boundary
P-Drive
N-Drive
UVLO
Thermal Limit
Current Limit
Soft Start
Sawtooth
Generator
(+)
(-)
PWM
Comp
PVIN
ENABLE
PGND
Logic
Compensation
Network
NC
(SW)
POK
POK
AVIN AGND
BIAS
TST
Figure 4: Functional Block Diagram
Functional Description
Overview
The EN5339QI is a highly integrated synchronous
buck converter with an internal inductor utilizing
advanced CMOS technology to provide high
switching frequency, while also maintaining high
efficiency. The EN5339QI is a high power density
device packaged in a tiny 4x6x1.1mm 24-pin QFN
package. Its high switching frequency allows for the
use of very small MLCC input and output filter
capacitors and results in a total solution size as
small as 55mm 2 .
The EN5339QI buck converter uses Type III
voltage mode control to provide pin-point output
voltage accuracy, high noise immunity, low output
impedance and excellent load transient response.
The EN5339QI features include Power OK, under
voltage lockout (UVLO), over current protection,
short circuit protection, and thermal overload
protection.
Stability and Compensation
The EN5339QI utilizes an internal compensation
network that is designed to provide stable operation
over a wide range of operating conditions. The
output compensation circuit may be customized to
improve transient performance or reduce output
voltage ripple with dynamic loads.
Soft-Start
The EN5339QI has an internal soft-start circuit that
controls the ramp of the output voltage. The control
circuitry limits the V
OUT
ramp rate to levels that are
safe for the Power MOSFETs and the integrated
inductor.
The EN5339QI has a constant startup up time
which is independent of the VOUT setting. The
output rising slew rate is proportional to the output
voltage. The startup time is approximately 1.4ms
from when the ENABLE is first pulled high until
VOUT reaches the regulated voltage level.
www.altera.com/enpirion , Page 11
06903 July 9, 2014 Rev D
75