DEC 4000 600 series, Руководство пользователя, Страница: 180 / 242

CPU Subsystem
CPU Subsystem
Components The CPU subsystem consists of the following components:
• System bus
• Central processing units (1 or 2)
• Memory modules (1 to 4)
• I/O module
System Bus
The system bus interconnects the CPUs, memory modules,
and I/O module. The I/O module provides access to basic I/O
functions (network, storage devices, and console program).
The I/O module also is the bridge to the I/O expansion bus,
Fu.
The system bus is a shared-memory bus designed to support the
Alpha AXP architecture and up to two processors. It supports a
‘‘snooping protocol’’ that allows a CPU’s first-level write-through
cache and second-level write-back cache to maintain consistent
data with another processor’s caches, system memory, and the
I/O port on a transaction-by-transaction basis.
The system bus is a synchronous, multiplexed interconnect that
can transfer a 34-bit address or a 128-bit data with 32-bit parity
in a single cycle. Two CPU modules and an I/O module arbitrate
for the system bus via a prioritized scheme that allows the I/O
module to interleave with the two CPU modules. The arbitration
function and system bus clock generators are located on the CPU
1 module.
Central
Processing Unit
The KN430 CPU module houses the DECchip 21064 processor
which implements the Alpha architecture. The system supports
up to two CPU modules in a symmetric multiprocessing
configuration.
The CPU controls the execution of all instructions and processes.
The CPU circuits contain the logic, arithmetic, and control
functions used by the system.
7–6 Learning More About Your System