Datum Systems M7 Series, Инструкция по установке и эксплуатации

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M7/M7L/M7LT Modular Satellite Modem Maintenance
M7/M7L/M7LT - Rev. 0.05 3-99
3.9.2.1. Demodulator Receive Data FIFO Operation
The modem has a built-in First-In First-Out (FIFO) buffer on the receive data channel that may be
enabled to compensate for cyclical variations in the receive data rate. Cyclical variations are most
often caused by the daily movement of the satellite in its position resulting in a varying distance from
earth station locations. This movement would cause the receive data rate to increase during a portion
of the day and decrease during other periods. This type of cyclic change is termed Doppler variation
and the buffer to absorb the variation is a Doppler Buffer. The setting of the FIFO buffer size will need
to accommodate these variations to prevent any data loss.
In certain network configuration typical in international Telco connections, there will be separate very
high stability clock standards that are not locked to each other. The FIFO at each end of the link will
be provided a local clock for the purpose of clocking the data out of the modem. A receive buffer used
to absorb this type of clock offset is referred to as a Plesiochronous buffer. This type of clock
difference is uni-directional and cumulative to the point that eventually there will be a FIFO buffer slip.
The severity of the disruption can be minimized by setting the buffer size in bits to multiples of the
frame size. For example if the total frame size is 512 bits and the buffer is set to a size of 1024 bits an
under or over-run would result in the frame flags remaining in the same location in the data stream.
Note that frames will still be errored by the under or over-run, but synchronization may not be lost. If a
superframe structure is used it is likely that synchronization will still be lost.
Other data rate variations between the transmitting and receiving stations which are not periodic, i.e.
do not average to zero, can be buffered by the FIFO, but will eventually result in lost data.
Refer to the discussion in Section 0 above for the selections available for clocking the data in and out
of the FIFO buffer.
The Receive FIFO operation can be set from the front panel or remote control, and consists of
selecting the
<Intf: I/O - Rcv Clock Source>
parameter to something other than “Dmd Rcv Clock”
and the <Intf: I/O - Rcv Buffer Delay> parameter to the desired delay in milliseconds. The processor
computes the <Intf: I/O - Rcv Buffer Size> parameter to the size of the FIFO in bits based on the
current data rate.
The modem processor also can display the current FIFO fill percentage status. The FIFO sets the
delay or number of bits selected upon activation and this center value represents 100% FIFO fill. At
any time the FIFO may contain from 0% to 200% of the set value. The percentage fill can also
represent the percentage of delay with respect to the setting. For example if the buffer was set to 2
mS of delay and the fill is 150% this represents 3 mS of delay.
When the data rate is changed the modem maintains delay time constant, automatically changing the
number of bits stored in the buffer to compensate.
NOTE: When the number of bits of delay are very small, one bit may represent a large percentage
change (e.g. if the delay is only 4 bits, each bit represents 25%). The delay may be set from 4
bits to 131,070 bits at any data rate, resulting in a delay ranging from 0.00081mS (4 bits at
4.92 Mbps) to over 42,000 mS (131,070 bits at 2400 bps).
An overrun occurs when a bit is clocked into the FIFO causing the fill to reach a full 200% of the
selected value. This causes flushing the upper half of the FIFO, restoring the fill to 100%, re-centering
the FIFO. The data flushed is lost and cannot be recovered.
An under-run occurs when the last bit is clocked out of the FIFO, emptying it. This also causes re-
centering of the FIFO by resetting the buffer pointers to the mid or 100% level, resending all the data
in the buffer. Both conditions result in a potential serious disruption of traffic.
When an under or over-run occurs an internal modem flag is set indicating that a re-center has
occurred. The front panel display shows “Slip” and FIFO fill data percentages read from the remote
port are negative numbers. This latched flag may be reset at the front panel or by writing to the
remote port FIFO parameter.