Xtium-CL PX4 User's Manual
Technical Specifications
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67
J2: Camera Link Connector 2
Medium and Full Camera Link sources require cables connected to both J2 and J3.
Name
Pin #
Type
Description
MEDIUM _X0-
25
Input
Neg. Medium Data 0
MEDIUM _X0+
12
Input
Pos. Medium Data 0
MEDIUM _X1-
24
Input
Neg. Medium Data 1
MEDIUM _X1+
11
Input
Pos. Medium Data 1
MEDIUM _X2-
23
Input
Neg. Medium Data 2
MEDIUM _X2+
10
Input
Pos. Medium Data 2
MEDIUM _X3-
21
Input
Neg. Medium Data 3
MEDIUM _X3+
8
Input
Pos. Medium Data 3
MEDIUM _XCLK-
22
Input
Neg. Medium Clock
MEDIUM _XCLK+
9
Input
Pos. Medium Clock
TERM
20
Term Resistor
TERM
7
Term Resistor
FULL_X0-
19
Input
Neg. Full Data 0
FULL _X0+
6
Input
Pos. Full Data 0
FULL _X1-
18
Input
Neg. Full Data 1
FULL _X1+
5
Input
Pos. Full Data 1
FULL _X2-
17
Input
Neg. Full Data 2
FULL _X2+
4
Input
Pos. Full Data 2
FULL _X3-
15
Input
Neg. Full Data 3
FULL _X3+
2
Input
Pos. Full Data 3
FULL _XCLK-
16
Input
Neg. Full Clock
FULL _XCLK+
3
Input
Pos. Full Clock
PoCL
1,26
+12 V (see note following table)
GND
13, 14
Ground
Table 29: Camera Link Connector 2
Notes on PoCL support:
Refer to Sapera’s parameter CORACQ_PRM_POCL_ENABLE to enable PoCL and
CORACQ_PRM_SIGNAL_STATUS/CORACQ_VAL_SIGNAL_POCL_ACTIVE_2 to verify if the POCL
is active. See also + reference parameter SapAcquisition::SignalPoCLActive for the
current state.
PoCL state is maintained as long as the board is not reset
