Dalsa Linea2 5GigE, Руководство пользователя

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Linea2 5GigE Series Camera Operational Reference • 71
Display Name Feature & Values Description Standard
& View
Valid Frame Start FrameStart Timer starts on the reception of the Frame Start event.
Frame Burst End FrameBurstEnd Timer starts with the reception of the Frame Burst End event.
Valid Frame Trigger ValidFrameTrigger Timer starts with the reception of Valid Frame Trigger event.
Valid Line Start LineStart Timer starts on the reception of the line start event.
Rejected Line Trigger InvalidLineTrigger Timer starts on the reception of the Invalid Line Trigger.
Timer 1 End Timer1End Start Timer on Timer 1 End event.
Timer 2 End Timer2End Start Timer on Timer 2 End event.
Counter 1 End Counter1End Start Timer on Counter 1 End event.
Counter 2 End Counter2End Start Timer on Counter 2 End event.
Timer Start Line
Activation timerStartLineActivation Select the trigger activation mode which starts the timer.
Expert
DFNC
Rising Edge RisingEdge Starts timer on the rising edge of the selected signal.
Falling Edge FallingEdge Starts timer on the falling edge of the selected signal.
Any Edge AnyEdge Starts timer on the falling or rising edge of the
selected signal.
Timer Duration (in us)
timerDuration Sets the duration (in microseconds) of the timer pulse.
Expert
DFNC
Timer Value timerValue Reads the current value (in microseconds) of the selected timer.
Expert
DFNC
Timer Reset timerReset Resets the timer to 0 while timerStatus=TimerActive. Timer
then waits for the next timerStartSource event.
Expert
DFNC
Counter and Timer Group Block Diagram
Line Selector =
Line 1 to 5
Physical
Line
Event Driven
Input
Inverter
Output
inverter
Software Driven
Pulse
Generator
LineStatus
Trigger
Line
Activation
Trigger Signal
Timer
TimerEnd Event
CounterEnd Event
Software Trigger
Cmd
Line
Mode
Input
or
Output
Input
Output
Timer and Counter Module
Counter
Line
Debouncer
Event Driven
Trigger
Source
Trigger Module
Output
Line
Source
Signal Driven
Software Driven
Line
Detection
Level
Figure 48: Counter and Timer Group Block Diagram