Cypress S29VS128R, Руководство пользователя

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Document Number: 002-00833 Rev. *L Page 37 of 74
S29VS256R
S29VS128R
S29XS256R
S29XS128R
7.7.6 Accelerated Program/Sector Erase
Accelerated write buffer programming, and sector erase operations are enabled through the V
PP
function. This method is faster than
the standard chip program and sector erase command sequences.
The accelerated write buffer program and sector erase functions must not be used more than 50 times per sector. In
addition, accelerated write buffer program and sector erase should be performed at room temperature (30°C ±10°C).
If the system asserts V
HH
on V
PP
, the device automatically uses the higher voltage on the input to reduce the time required for
program and erase operations. Removing V
HH
from the V
PP
input, upon completion of the embedded program or erase operation,
returns the device to normal operation.
 Simultaneous operations are not supported while V
PP
is at V
HH
. The V
PP
pin must not be at V
HH
for operations other than
accelerated write buffer programming, accelerated sector erase, and status register read or device damage may result.
 The V
PP
pin must not be left floating or unconnected; inconsistent behavior of the device may result.

There is a minimum of 100 ms required between accelerated write buffer programming and a subsequent accelerated sector
erase.
7.8 Handshaking
The handshaking feature allows the host system to detect when data is ready to be read by simply monitoring the RDY (Ready) pin,
which is a dedicated output controlled by CE#.
When CE# input is Low, the RDY output signal is actively driven. When both of the CE# inputs are High the RDY output is
high-impedance. When CE# input and OE# input is Low, the A/DQ15-A/DQ0 output signals are actively driven. When both of the
CE# inputs are High, or the OE# input is High, the A/DQ15-A/DQ0 outputs are high-impedance.
When the device is operated in synchronous mode, and OE# is low (active), the initial word of burst data becomes available after the
rising edge of the RDY. CR.8 in the Configuration Register allows the host to specify whether RDY is active at the same time that
data is ready, or one cycle before data is ready (see
Table 20 on page 24 ).
When the device is operated in asynchronous mode, RDY will be high when CE# is low (active).
7.9 Hardware Reset
The RESET# input provides a hardware method of resetting the device to idle state. When RESET# is driven low for at least a period
of t
RP
, the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and
ignores all read/write commands for the duration of the reset operation. The device also resets the internal state machine to idle
state. Hardware Reset clears the AADM upper address register to zero.
To ensure data integrity the operation that was interrupted should be reinitiated once the device is ready to accept another
command sequence.
When RESET# is held at V
SS
, the device draws CMOS standby current (I
CC4
). If RESET# is held at V
IL
, but not at V
SS
, the standby
current is greater.
See Figure 16 for timing diagrams
7.10 Software Reset
Software reset is part of the command set (see Table 43 on page 57 ) that also returns the device to idle state and must be used for
the following conditions:
1. Exit ID/CFI mode
2. Exit Secure Silicon Region mode
3. Exit Configuration Register mode
4. Exit SSR Lock mode
Reset commands are ignored once programming/erasure has begun until the operation is complete.