Document Number: 002-00833 Rev. *L
Page 9 of 74
S29VS256R
S29VS128R
S29XS256R
S29XS128R
6.
Address Space Maps
There are five address spaces within each device:
A Non-Volatile Flash Memory Array used for storage of data that may be randomly accessed by asynchronous or burst read
operations.
A Read Only Memory Array used for factory programmed permanent device characteristics information. This area contains the
Device Identification (ID) and Common Flash Interface (CFI) information.
A One Time Programmable (OTP) Non-volatile Flash array used for factory programmed permanent data, and customer
programmable permanent data. This is called the Secure Silicon Region (SSR).
An OTP location used to permanently protect the SSR. This is call the SSR Lock.
A volatile register used to configure device behavior options. This is called the Configuration Register.
The main Flash Memory Array is the primary and default address space but, it may be partially overlaid by the other four address
spaces with one alternate address space available at any one time. The location where the alternate address space is overlaid is
defined by the address provided in the command that enables each overlay. The portion of the command address that is sufficient to
select a sector is used to select the sector that is overlaid by an alternate Address Space Overlay (ASO).
Any address range, within the overlaid sector, not defined by an overlay address map, is reserved for future use. All read accesses
outside of an address map within the selected sector, return non-valid data. The locations will display actively driven data but the
meaning of whatever ones or zeros appear are not defined.
There are three operation modes for each bank that determine what portions of the address space are readable at any given time:
Read Mode
Embedded Algorithm (EA) Mode
Address Space Overlay (ASO) Mode
Each bank of the device can be in any operation mode but, only one bank can be in EA or ASO mode at any one time.
In Read Mode, a Flash Memory Array bank may be directly read by asynchronous or burst accesses from the host system bus. The
Control Unit (CU) puts all banks in Read mode during Power-on, a Hardware Reset, after a Command Reset, or after a bank is
returned to Read mode from EA mode.
In EA mode the Flash memory array data in a bank is stable but undefined, and effectively unavailable for read access from the host
system. While in EA mode the bank is used by the CU in the execution of commands. Typical EA mode operations are programming
or erasing of data in the Flash array. All other banks are available for read access while the one bank is in EA mode. This ability to
read from one bank while another bank is used in the execution of a command is called Simultaneous Read and Write (SRW) and
allows for continued operation of the system via the reading of data or execution of code from other banks while one bank is
programming or erasing data as a relatively long time frame background task.
In ASO mode, one of the overlay address spaces are overlaid in a bank (entered). That bank is in ASO mode and no other bank may
be in EA or ASO mode. All EA activity must be completed before entering any ASO mode. A command for entering an EA or ASO
mode while another bank is in EA or ASO mode will be ignored.
While an ASO mode is active (entered) in a bank, a read for Flash array data to any other bank is allowed. ASO mode selects a
specific sector for the overlaid address space. Other sectors in the ASO bank still provide Flash array data and may be read during
ASO mode.
The ASOs are functionally tied to the lowest address bank. The commands used to overlay (enter) these areas must select a sector
address within the lowest address bank.
While SSR Lock, SSR, or Configuration Register is overlaid only the SSR Lock, SSR, or Configuration Register respectively may be
programmed in the overlaid sector. While any of these ASO areas are being programmed the ASO bank switches to EA mode. The
ID/CFI and factory portion of the SSR ASO is not customer programmable.
The address nomenclature used in this document is a shorthand form that shows addresses are formed from a concatenation of
high order bits, sufficient to select a Sector Address (SA), with low order bits to select a location within the sector. When in Read
mode and reading from the Flash Array the entire address is used to select a specific word for asynchronous read or the starting
word address of a burst read. When writing a command, the address bits between SA and the command specified least significant
bits must be Zero to allow for future extension of an overlay address map.
