Document Number: 002-00833 Rev. *L
Page 23 of 74
S29VS256R
S29VS128R
S29XS256R
S29XS128R
Figure 4. Synchronous Read
7.2.5
Configuration Register
Configuration register (CR) sets various operational parameters associated with burst mode. Upon power-up or hardware reset, the
device defaults to the idle state, and the configuration register settings are in their default state. The host system should determine
the proper settings for the configuration register, and then execute the Set Configuration Register command sequence, before
attempting burst operations. The Configuration Register can also be read using a command sequence (see
).
The table below describes the register settings and indicates the default state of each bit after power-on or a hardware reset. The
configuration register bits are not affected by a command reset.
Load Initial Address
Address = RA
Read Initial Data
RD = DQ[15:0]
Read Next Data
RD = DQ[15:0]
Wait Programmable
Wait State Setting
Wait X Clocks (if required):
Additional Latency Due to Starting
Address and Clock Frequency
End of Data?
Yes
Crossing
Boundary?
No
Yes
Completed
RA = Read Address
RD = Read Data
CR0.14 - CR0.11 sets initial access time
(from address latched to
valid data) from 3 to 13 clock cycles
No
