Document Number: 002-00833 Rev. *L
Page 42 of 74
S29VS256R
S29VS128R
S29XS256R
S29XS128R
/* Example: SecSi Sector Exit Command */
*( (UINT16 *)bas 0x000 ) = 0x00F0; /* write SecSi Sector Exit cycle */
9.
Power Conservation Modes
9.1
Standby Mode
In the standby mode current consumption is greatly reduced, and the outputs (A/DQ15-A/DQ0) are placed in the high impedance
state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at
V
CC
± 0.2 V. The device requires standard access time (t
CE
or t
IA
) for read access, before it is ready to read data. If the device is
deselected during erasure or programming, the device draws active current until the operation is completed. I
CC3
in
represents the standby current specification
9.2
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption while in asynchronous mode and while the device is not in a
suspended state. The device automatically enables this mode when addresses remain stable for t
ACC
+ 20 ns. The automatic sleep
mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings (t
ACC
or t
PACC
) provide new data
when addresses are changed. While in sleep mode, output data is latched and always available to the system. While in synchronous
mode, the automatic sleep mode is disabled. I
CC6
in
represents the automatic sleep mode current
specification.
9.3
Output Disable (OE#)
When the OE# input is at V
IH
, output (A/DQ15-A/DQ0) from the device is disabled and placed in the high impedance state. RDY is
not controlled by OE#.
Table 40. Secured Silicon Region Exit
Cycle
Operation
Byte Address
Word Address
Data
Exit Cycle
Write
Base Address
Base Address
00F0h
