Crystal CS4281, Руководство по программированию

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CS4281 Programming Manual
DS308PRM1 202
Confidential Draft 3/7/00
21.2 Initialization
On a hardware reset, if
SPMC.EESPD
is clear, a hard-
ware-based EEPROM controller steps through the
following sequence to initialize the CS4281:
CS4281 Initialization
• Enable EEPROM interface (switches mode
of EECLK pin).
• Send a dummy write to set the byte address
to 0.
• Start sequential read of bytes from
EEPROM.
• Check signature header as loaded; abort if
an invalid signature is detected.
• Load fixed number of bytes, transferring
data into destination configuration bits as
loaded.
The only time when the CS4281 accesses the EE-
PROM is after a hardware reset; the CS4281 can
only read EEPROM devices — it cannot write
them unassisted. Writing a EEPROM can be ac-
complished through a configuration interface reg-
ister accessible from the host. The timing of the
data and clock signals for the initialization load are
generated by a hardware state machine. The mini-
mum timing relationship between the clock and
data is shown in the figure below. The state of the
data line can change only when the clock line is
low. A state change of the data line during the time
that the clock line is high is used to indicate start
and stop conditions.
The EEPROM device read access sequence is
shown in the figure below. The timing follows that
of a random read sequence. The CS4281 first per-
forms a dummy write operation, generating a start
condition followed by the slave device address and
an byte address of zero. The slave address is made
up of a device identifier (0xA) and a bank select
(bits A2-A0). The bank select bits select among
eight 256 byte blocks. The bank select bits may be
used to select among multiple 256 byte blocks
within a single device, i.e. a 1 kbyte memory may
be comprised of a single 1 kbyte EEPROM with
four 256 byte banks. The CS4281 always begins
access at byte address zero and continues accessing
one byte at a time. In the EEPROM, the byte ad-
dress automatically increments by one until a stop
condition is detected.
CLOCK
DATA IN
4.0us
4.7us
250ns
0ns
DATA
SETUP
DATA
HOLD
CLOCK
HIGH
CLOCK
LOW
4.7us
START
START
HOLD
4.0ns
DATA OUT
3.5us
tR 1000ns
<>
tF 300ns
<
STOP
SETUP
4us
us
Figure 58. EEPROM timing requirements
S 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0
S 1 0 1 0 0 0 0 Data Data
0 A
A 1 A A 1 P
St
ar
t
Slave
Addr
W
rite
Ack
Byte
Addr 0
Ack
St
ar
t
Slave
Addr
R
ead
Ack
Ac
k
No
Ack
St
o
p
Figure 59. EEPROM read sequence
D
ra
ft