Crystal CS4281, Руководство по программированию

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Confidential Draft 3/7/00
CS4281 Programming Manual
86 DS308PRM1
that the DMAn/FIFOn combination is in DMA
mode, and
DMRn.POLL
indicates that the
DMAn/FIFOn connection is in Polled FIFO mode.
The
DMA
and
POLL
bits are mutually exclusive.
When
DMA
or
POLL
goes from a 0 to a 1, the
DMAn engine is set in it’s initial state (channel sta-
tus cleared). For either mode, the
FCRn.FEN
bit
must be set to enable the FIFO.
11.1.1 Host Interrupts for DMA Mode
There is a global mask/interrupt bit for DMA gen-
erated interrupts and individual mask bits for each
engine. DMA interrupts are masked through the
Host Interrupt Mask Register, HIMR, and the inter-
rupt status is reported in the Host Interrupt Status
Register, HISR.
When a FIFOn/DMAn pair is setup for DMA (
DM-
Rn.DMA
set), interrupts can be generated from ei-
ther Terminal Count or Half Terminal Count. The
logic diagram for DMA interrupts is illustrated in
Figure 21. The upper word of DCRn provides en-
able bits for each interrupt. Interrupt status for indi-
vidual DMAn engines is located in the HDSRn
register. Reading the upper word of HDSRn clears
the interrupt condition/status (after read). As an ex-
ample, if the HISR indicates that DMA1 caused the
interrupt (
HISR.DMA1
), the interrupt condition is
cleared by reading HDSR1.
11.1.2 Host Interrupts in FIFO Polling
Mode
Host interrupts can also be generated for Polled
FIFO modes. All interrupts are masked through the
Host Interrupt Mask Register, HIMR, and the inter-
rupt status is reported in the Host Interrupt Status
Register, HISR. There is a global mask/interrupt bit
for Polled FIFO mode and individual mask bits for
each FIFO.
The FIFO interrupt logic, shown in Figure 22, can
generate interrupts as long as the particular FIFO is
enabled (
FCRn.FEN
). Generally, FIFO interrupts
would only be enabled in Polled FIFO mode. The
FSICn.FSC[6:0]
bits contain the current sample
count for the FIFO (number of samples currently in
the FIFO). An interrupt can be generated when the
FSICn.FSC
bits match the host programmed
FSICn.FIC
bits. The
FIFOn.FIC
bits can be pro-
grammed to generated an interrupt on any FIFO
depth such as:
• FIFO Empty:
FSICn.FIC[6:0]
= 0
• FIFO Not Empty:
FSICn.FIC[6:0]
= 1
• FIFO Half Full:
FSICn.FIC[6:0]
=
FCRn.SZ
/2
• FIFO Not Full:
FSICn.FIC[6:0]
=
FCRn.SZ
- 1
• FIFO Full:
FSICn.FIC[6:0]
=
FCRn.SZ[6:0]
Two error conditions can also generate interrupts.
FIFO Overrun,
FSICn.FOR
, indicates that, pending
on FIFO direction, either the Bus Interface side
S
R
Q
DCRn.HTCIE
HISR.DMAI
DCRn.TCIE
DMAn Half
Terminal Count
Pulse
HDSRn.DHTC
OR with other
interrupt sources
HIMR.DMAIM
Other 3 DMA
channels
HIMR.DnIM
HISR.DMAn
HDSRn.DTC
S
R
Q
DMAn Terminal
Count Pulse
DMRn.DMA
End of HDSRn upper byte
Register Read
Figure 21. DMA Interrupt Conceptual Logic
D
ra
ft