Crystal CS4281, Руководство по программированию

Страница: 126 / 231

Confidential Draft 3/7/00
CS4281 Programming Manual
126 DS308PRM1
7 are snooped and, when read or
written,
IOTCC.BPFF
is toggled. In addition, one set
of legacy DMA registers in the same address range
can be trapped or snooped based on the IOTCC
bits
C1RE
,
C1WE
, and
C1WSE
. Only one of the four
sets of registers responds based on the
IOTCR.DMA[1:0]
bits. Using legacy DMA3 for
example, a typical setup scenario would be:
• Game software writes xxh to address 0Ch
• 0Ch snooped and
IOTCC.BPFF
cleared.
• Game software then writes lower address byte
to Base address register - 06h
• 06h trapped/snooped and (since
BPFF
= 0) data written to
DBA3.BAL[7:0]
and
DCA3.CAL[7:0]
.
•
BPFF
toggled (XOR’d) - now
BPFF
= 1
• Game software then writes upper address byte
to Base address register - 06h
• 06h trapped/snooped and (since
BPFF
= 1) data written to
DBA3.BAH[7:0]
and
DCA3.CAH[7:0]
.
•
BPFF
toggled (XOR’d) - now
BPFF
= 0
• Game software then writes lower count byte to
Base count register - 07h
• 07h trapped/snooped and (since
BPFF
= 0) data written to
DBC3.BCL[7:0]
and
DCC3.CCL[7:0]
.
•
BPFF
toggled (XOR’d) - now
BPFF
= 1
• Game software then writes upper count byte to
Base count register - 07h
• 07h trapped/snooped and (since
BPFF
= 1) data written to
DBC3.BCH[7:0]
and
DCC3.CCH[7:0]
.
•
BPFF
toggled (XOR’d) - now
BPFF
= 0
• Game software then writes DMA3 page
register - 82h
82h trapped/snooped and data
written to
DBA3.BAU[15:0]
and
DBA3.CAU[15:0]
.
Note that the upper byte is forced to 0 and the
data written goes into the lower byte.
• Since this example uses DMA3, addresses
between 0 and 5 are snooped. Any reads or
writes toggle
BPFF
.
The third set of legacy DMA registers consist of
two write-only registers, Single Mask and Mode;
where the lower two bits determine the mapping to
CS4281 DMAn registers DCRn and DMRn,
respectively. Trapping for these registers is
controlled through the
IOTCC.C3WSE
bit, which
only allows write snooping. Write trapping is not
supported since these registers are shared by all
legacy DMA controllers. Read trapping is not
supported since these registers are write-only.
Figure 40 illustrates the logic decoding for the
Mode register. The lower two data bits are
compared to the
IOTCR.DMA
bits. If they match
(and CCLS enabled), the data is written into the
lower byte of the DMRn register assigned to
legacy support.
Figure 41 illustrates the conceptual logic for the
Single Mask register. The lower two data bits are
compared to the
IOTCR.DMA
bits. If they match
(and CCLS enabled), then Single Mask bit 2 is
redirected to
DCRn.MSK
in the bit 0 position.
DCRn.MSK
is in the 0
th
bit position to support
DDMA operation.
The fourth set of legacy DMA registers consist of
one read-only register, one read-write register, and
one write-only register, Status, All Mask, and
Clear-All Mask; where reading two of these
registers requires the CS4281 to force a host retry.
Then the CS4281 must go set status from the real
8237 and combine that with the CS4281’s legacy
engine. Then when the host retries, the CS4281
returns the combined status. Trapping for these
registers is controlled through the
IOTCC.C4xxx
bits,
which support read trapping and write snooping.
Write trapping is not supported since these
registers are shared by all legacy DMA controllers
and snooping can accomplish the same task. Read
trapping (for Status and All Mask registers)
requires host retries and assumes the only other
device interested in legacy DMA is a subtractive
bridge. Note that this method of trapping will not
work with positive decode bridges (such as the
D
ra
ft