Crystal CS4281, Руководство по программированию

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CS4281 Programming Manual
DS308PRM1 225
Confidential Draft 3/7/00
23. TEST
The Testability Block contains all the normal test
functions and the special purpose test features.
The test functions are separated into two
categories - those that can be run in the system are
the Normal Test Functions, and those that must be
in a special test fixture or evaluation board are
Special Test Functions. In addition to these
functions there are several observation registers in
the PCI space that are used to observe the behavior
of internal state machines.
With the elimination of the internal 8052, the pin
remapping that was used is not needed. The only
pin remapping needed is to support the scan
testing and clock multiplier bypass/monitor
testing. The joystick button and coordinate pins
will be used for the scan test. The
VOLUP
and
VOLDN
pins will be used for the clock multiplier
testing. The joystick button and
MIDIIN
pins select
the test mode when using hardware test mode
entry.
23.1 Normal Test Modes
• RAM/ROM test
• MIDI loopback - MIDI out - MIDI in
• SRC loopback - PCI - FIFO - SRC - FIFO - PCI
• Primary AC Link Loopback - PCI - FIFO -
ASDOUT - ASDIN - FIFO - PCI
• Secondary AC Link Loopback - PCI - FIFO -
ASDOUT - ASDIN2 - FIFO - PCI
• Joystick comparator test
• Fast Count
Special Test Modes
• Force all outputs low
• Force all outputs high
• Force all outputs float
• Input XOR tree
• Bypass clock multiplier, input 512
×
fs clock
• DLL monitor
• Scan Test
23.2 Boundary Test Mode
The Boundary Test Mode is a the same as the
Special Test Mode 4, Input XOR Tree Test. A
simplified entry procedure is provided. The
Boundary Test Mode is entered by asserting the
TEST
pin high with the
TESTSEL
pin high. The
part will remain in the Boundary Test Mode until
the
TEST
pin is deasserted. See the Input XOR
Tree description for the specific functional
behavior.
23.3 Normal Test mode Entry
Normal Test Modes are entered by software or
hardware mechanisms. Software test selection is
setup by writing the desired mode selection to the
Test Select Register, PCI Configuration F8h and
setting the
IISR.TMSE
bit. Hardware test selection is
setup by the code on the Joystick Button pins and
the
MIDIIN
pin, with the Test Select Register zero.
The test is entered by either asserting the
TEST
pin
or writing the Test Enable Bit Pattern. The test
mode is exited by writing zeros to the Test Select
Register, deasserting the
TEST
pin, or by changing
the Test Enable Bit Pattern. The Test Enable Bit
Pattern is implemented by a set of reserved bits
spread among two different registers. The intent is
that the test condition cannot be entered
accidently, and be very difficult to hack. The Test
Select Register will be reserved also. Test Select
value of zero is a no test condition, normal
operation.
23.4 Special Test Mode Entry
Special Test Modes should only be entered
through hardware, since they will operate only in a
special fixture, or on an isolated bus. The desired
test function is selected by the code applied to the
Joystick Button pins, the
TESTSEL
pin is held low,
and then the
TEST
pin is asserted high. The test
mode is exited by deasserting the
TEST
pin. A
value of all zeros on the test select pins is a no test
D
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