Crystal CS4281, Руководство по программированию

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Confidential Draft 3/7/00
CS4281 Programming Manual
196 DS308PRM1
20.4.3 Host MIDI Command Register (MIDCMD)
Address: BA0: 494h, Write-Only
Default: 00000000h
Definition: A host command port for the MPU-401 functions. This register has no effect and is provided for
backwards compatibility.
Bit Descriptions:
CS[7:0] The MPU-401 Command Register.
20.4.4 Host MIDI Status Register (MIDSR)
Address: BA0: 494h, Read-Only
Default: 00000080h
Definition: Host status port for the MIDI input and output ports.
Bit Descriptions:
CS[5:0] The 6 LSBs of the last command written to the Command Register.
TBF Transmit Buffer Full: This bit returns the full/not full status of the MIDI transmit FIFO.
0 = FIFO not full (reset default)
1 = FIFO full
RBE Receive Buffer Empty: This bit returns the empty/not empty status of the MIDI receive FIFO.
0 = FIFO not empty
1 = FIFO empty (reset default)
TBE This bit is sticky and is set when the
TBF
flag transitions from a 1 to a 0 and is cleared by
reading this register.
TBE
is forced to 0 by
MIDCR.TIE
= 0. This bit is OR’d with
RDA
and
reflected in the Interrupt Status register,
HISR.MIDI
bit. See Figure 54.
RDA This bit is sticky and is set when the
RBE
flag goes from a 1 to a 0 (data available) and cleared
by reading this register.
RDA
is forced to 0 by
MIDCR.RIE
= 0. This bit is OR’d with
TBE
and
reflected in the Interrupt Status register,
HISR.MIDI
. See Figure 54.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDA TBE RBE TBF CS5 CS4 CS3 CS2 CS1 CS0
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