Crystal CS4281, Руководство по программированию

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CS4281 Programming Manual
DS308PRM1 57
Confidential Draft 3/7/00
8. START-UP CONFIGURATION AND
STATUS
8.1 PCI Start-Up Configuration
PCI configuration of the CS4281 is generally han-
dled by standard PCI setup BIOS code or operating
system code. This code loads the standard configu-
ration space with BA0 and BA1 address to allocate
the memory needed by the CS4281. Other CS4281-
specific registers exist in Config Space that BIOS
or configuration code must set to let the CS4281
Driver and operating system know that those fea-
tures exist in the system as configured. Those extra
setup issues are enumerated below. Note that all
configuration space data at 00-FFh in config space
can also be read and, all locations above 44h, writ-
ten in host memory space BA0:300h - BA0:3FFh.
In config space, locations above 44h are write-pro-
tected by the CWPR register located at CFG:0EEh,
which must be programmed to 4281h before any of
the vendor defined configuration registers can be
written.
• To write any of the vendor defined
configuration registers (above CFG: 044h),
write CWPR to 4281h
• Microsoft Win 95/98 OS requires a non-zero
SSID and SSVID at PCI config. location 2Ch-
2Fh. For the CS4281, this register can be
loaded through PCI config locations FCh-FFh
which will show up as read-only at 2Ch-2Fh.
These can be loaded in 2 ways:
• EEPROM bytes 1-4. If EEPROM byte 0 is
55h, the CS4281 will auto-load EEPROM
bytes 1-4 into PCI config space FCh-FFh.
• BIOS loads bytes at Config Space location
FCh-FFh.
• CFLR bits indicate configuration data. The
CS4281 supports the CS4280/4614/4622/4624
(Inky) 2 bytes, plus two additional bytes. The
bytes are loaded into the CFLR register at PCI
config. location F0h, where F0h and F1h are
Inky’s CFL1 and CLF2 respectively. Bytes at
locations F2h and F3h are new to the CS4281.
These four bytes can also be loaded via two
methods. Note that the Inky CFL1 and CFL2
registers are combined and moved from their
old BA0 locations of 414h and 418h, to the
CS4281 CFLR register mapped to BA0:3F0.
• EEPROM bytes 5-8. If EEPROM byte 0 is
55h, the CS4281 will auto-load EEPROM
bytes 5-8 into PCI config space F0h-F4h.
• BIOS can load the CFLR register (32 bits)
at PCI Config location F0h-F4h directly.
• ISA interrupts. BIOS needs to indicate which
ISA interrupt pins are connected and are
available for use through the IISR register at
PCI config. location F4h-F8h. Each ISA
interrupt pin has a corresponding four bits that
must be programmed to non-zero values if
used. The BIOS code should load the actual
interrupt number into the respective bits in
IISR:
IRQA[3:0]
,
IRQB[3:0]
,
IRQC[3:0]
. The
driver uses this information to decide which
interrupts are connected. Setting these bits does
not actually enable the ISA interrupt (still high
impedance). The driver enables the ISA
interrupt (to drive the pin) by have these bits
non-zero and enabling the interrupt through the
IIER register. IISR also contains three generic
flags that are maintained through a D3
cold
transition. Note that Inky uses a coded
configuration for ISA interrupt support through
the CFL2 bits.
• V
AUX
power. On the CS4281 V
AUX
power is
not auto-detected. The default configuration
assumes that the
VAUX
power pin is attached to
a core power supply that is not maintained in a
D3
cold
state. If the
VAUX
pin is attached to a
real V
AUX
3 V power supply, the following bits
must be programmed:
• PME# from D3
cold
supported. BIOS
should set
IISR.VAUXS
which will show up
as
PMC.PMD3C
.
D
ra
ft