EES3 Hardware Interface Description
2.3 Circuit Concept
22
EES3_HD_v01.100b
Page 22 of 118
2009-08-12
Confidential / Released
2.3
Circuit Concept
shows a block diagram of the EES3 module and illustrates the major functional com-
ponents:
Baseband block:
•
Digital baseband processor with DSP
•
Analog processor with power supply unit (PSU)
•
Flash / PSRAM (stacked)
•
Application interface (SMT with connecting pads)
RF section:
•
RF transceiver
•
RF power amplifier
•
RF front
•
Antenna pad
Figure 2:
EES3
block diagram
BATT+
GND
IGT
EMERG_OFF
ASC(0)
SIM Interface
D(0:15)
A(0:24)
RD; WR; CS; WAIT
Interface
RF - Baseband
NTC
BATT_TEMP
SYNC
RF
Transceiver
RF
Power Amplifier
PSRAM
Nor-Flash
Audio analog
USB
I2C/SPI
SPI
VEXT
ISENSE
VSENSE
VCHARGE
CHARGEGATE
TEMP1
REFCHG
ASC(1)
26MHz
RF
Front End
DAI
PWR_IND
Measuring
Network
32.768
kHz
26MHz
Appli
ca
tio
n
In
te
rface
Digital and Analog
Baseband Processor
Conversion
Switch
TEMP2
BATTEMP
AUXADC1
Several
Power supply
voltages
VDDLP