Document type:
Title:
Revision date:
Revision:
User's Manual (MUT)
Mod. V1495 General Purpose VME Board
12/02/2010
8
NPO:
Filename:
Number of pages:
Page:
00117/04:V1495.MUTx/08 V1495_REV8.DOC
42
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5. V1495 USER FPGA Reference Design Kit
5.1. Introduction
The CAEN V1495 board provides a user-customizable FPGA (called USER FPGA).
The COIN_REFERENCE reference design illustrates how to use the USER FPGA to
implement a Coincidence Unit & I/O Register Unit. This design can be customised by the
user in order to adapt its functionality to his own needs.
USER-DEFINED
LOGIC
HARDWARE ABSTRACTION LAYER
CA
EN
L
O
CA
L B
U
S
MEZZANINE
CARD
ON SLOT
D
MEZZANINE
CARD
ON SLOT
E
MEZZANINE
CARD
ON SLOT
F
ON-BOARD DELAY LINES
Port A (32 IN ECL/LVDS)
Port B (32 IN ECL/LVDS)
Port C (32 OUT LVDS)
Fig. 5.1: USER FPGA block diagram
5.2. Design
Kit
5.2.1. V1495HAL
The V1495 Hardware Abstraction Layer (V1495HAL) is a HDL module provided, in
Verilog format at netlist level, in order to help the hardware interfacing.
