Document type:
Title:
Revision date:
Revision:
User's Manual (MUT)
Mod. V1495 General Purpose VME Board
12/02/2010
8
NPO:
Filename:
Number of pages:
Page:
00117/04:V1495.MUTx/08 V1495_REV8.DOC
42
26
Reading from a register:
In case of a read operation from a register via VME, the datum to be returned must drive
the REG_DOUT and be stable on the CLK leading edge, where REG_RDEN is active.
The register access is valid only when USR_ACCESS is at logic level = 1.
5.3.3.
V1495 Front Panel Ports (PORT A,B,C,G) INTERFACE
These signals allows to handle the interface with the motherboard ports A, B, C, G.
A_DIN and B_DIN signals show the logic level of A and B ports (32 bit, input only).
The output logic level on port C can be set via C_DOUT signal.
The logic level on port G (LEMO connectors) can be set via G_LEV signal; the direction
via G_DIR, the datum to be written via G_DOUT or to be read via G_DIN.
5.3.4. V1495
Mezzanine
Expansion
Ports (PORT D,E,F) INTERFACE
These signals allows to handle the interface with the piggy back board ports D, E, F.
The following table explains the available signals:
Table 5.2: V1495 Mezzanine Expansion Ports signals
Port: Signal:
Function:
Applies
to:
D_DIR Selects
direction
Bidirectional
port
D_DIN
Read the logic level
Input/Bidirectional
D_DOUT
Set the logic level
Output/Bidirectional
D_ IDCODE Read IDCODE for piggy back identification
All
D
D_LEV
Set the logic level
Output/Bidirectional
E_DIR Selects
direction
Bidirectional
port
E_DIN
Read the logic level
Input/Bidirectional
E_DOUT
Set the logic level
Output/Bidirectional
E_ IDCODE Read IDCODE for piggy back identification
All
E
E_LEV
Set the logic level
Output/Bidirectional
F_DIR Selects
direction
Bidirectional
port
F_DIN
Read the logic level
Input/Bidirectional
F_DOUT
Set the logic level
Output/Bidirectional
F_ IDCODE Read IDCODE for piggy back identification
All
F
F_LEV
Set the logic level
Output/Bidirectional
5.3.5.
PDL Configuration Interface
PDL Configuration Interface signals are as follows:
Table 5.3: PDL Configuration Interface signals
PDL_WR OUT
1
Write
Enable
PDL_SEL
OUT
1
PDL Selection (0=>PDL0, 1=>PDL1)
PDL_READ IN
8
Read
Data
PDL_WRITE OUT
8
Write
Data
PDL_DIR
OUT
1
Direction (0=>Write, 1=>Read)
