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User's Manual (MUT)
Mod. V1495 General Purpose VME Board
12/02/2010
8
NPO:
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00117/04:V1495.MUTx/08 V1495_REV8.DOC
42
29
The following table illustrates the the register map of the USER FPGA reference design
(COIN_REFERENCE).
Table 5.7: COIN_REFERENCE register map
NAME
ADDRESS
DATA SIZING
ACCESS
NOTES
DEFAULT
A_STATUS_L
0x0000
D16
RO
Port A status. This register reflects
A[15:0] bit status.
A_STATUS_H
0x0002
D16
RO
Port A status. This register reflects
A[31:16] bit status.
B_STATUS_L
0x0004
D16
RO
Port B status. This register reflects
B[15:0] bit status.
B_STATUS_H
0x0006
D16
RO
Port B status. This register reflects
B[31:16] bit status.
C_STATUS_L
0x0008
D16
RO
Port C status. This register reflects
C[15:0] bit status.
C_STATUS_H
0x000A
D16
RO
Port C status. This register reflects
C[31:16] bit status.
A_MASK_L 0x000C D16
WO Port
A
mask.
This
register
masks
A[15:0].
Mask bit is active low.
X"FFFF"
A_MASK_H
0x000E
D16
WO
Port A mask. This register masks
A[31:16].
Mask bit is active low.
X"FFFF"
B_MASK_L
0x0010
D16
WO
Port B mask. This register masks
B[15:0].
Mask bit is active low.
X"FFFF"
B_MASK_H
0x0012
D16
WO
Port B mask. This register masks
B[31:16].
Mask bit is active low.
X"FFFF"
C_MASK_L
0x0014
D16
WO
Port C mask. This register masks
C[15:0].
Mask bit is active low.
X"FFFF"
C_MASK_H 0x0016 D16
WO
Port C mask. This register
masks C[31:16].
Mask bit is active low.
X"FFFF"
GATEWIDTH
0x0018
D16
WO
Gate signal width. This number
represents a multiple of the
X"0004"