Document type:
Title:
Revision date:
Revision:
User's Manual (MUT)
Mod. V1495 General Purpose VME Board
12/02/2010
8
NPO:
Filename:
Number of pages:
Page:
00117/04:V1495.MUTx/08 V1495_REV8.DOC
42
25
PORT NAME
DIRECTION
WIDTH
DESCRIPTION
PDL0_IN
OUT
1
Signal to PDL0
PDL1_IN
OUT
1
Signal to PDL1 Input
DLO0_GATE
OUT
1
Signal to DLO0 Input
DLO1_GATE
OUT
1
Signal to DLO1 Input
SPARE INTERFACE
SPARE_OUT
OUT
12
SPARE Data Out
SPARE_IN
IN
12
SPARE Data In
SPARE_DIR OUT
1
SPARE
Direction
LED INTERFACE
RED_PULSE
OUT
1
RED Led Pulse (active high)
GREEN_PULSE OUT
1
GREEN Led Pulse (active high)
5.3. Interface
description
5.3.1. Global
Signals
The nLBRES must be used as an asynchronous reset signal by the user. An active low
pulse will be generated when a write is done at the
Module Reset register address (see
§ 4.1).
The LBCLK is a 40 MHz clock. It is the FPGA main clock.
5.3.2. REGISTER
INTERFACE
The signals of the Register Interface allows to read/write into the USER FPGA registers,
which can be accessed via VMEbus. The COIN_REFERENCE module shows how to
implement a set of registers.
The following table shows the registers map as it is provided. Each register address is
coded via constants in V1495pkg.vhd file. This file allows to modify the registers map; all
registers allow D16 accesses (write only, read only or read/write). Registers default value
is the value after a reset for write only and read/write registers; read only registers return
the status of the signals read by the FPGA and have no default value.
The Register Interface allows to abstract the VME registers access. The User can access
a simple register interface: two signals (REG_WREN e REG_RDEN) are pulses with a
one clock cycle duration which enables respectively a write or a read access to a
register. REG_ADDR signal represents the register address.
Writing into a register:
In case of a write operation into a register via VME, the 16 bit datum is available through
the REG_DIN signal. The datum is guaranteed stable on the CLK leading edge where
REG_WREN is active. The register access is valid only when USR_ACCESS is at logic
level = 1.
