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Avnet Electronics Marketing
2 of 33
Rev 1.0 04/17/2006
Released
Literature # ADS-005104
Table of Contents
1.0 Introduction ............................................................................................................................................................................... 4
1.1 Description............................................................................................................................................................................ 4
1.2 Features: .............................................................................................................................................................................. 4
1.3 Demo
Applications:............................................................................................................................................................... 5
1.4 Ordering
Information:............................................................................................................................................................ 5
2.0 Hardware .................................................................................................................................................................................. 5
2.1 Spartan-3 FPGA ................................................................................................................................................................... 6
2.2 Configuration ........................................................................................................................................................................ 6
2.3 Jumper Settings.................................................................................................................................................................. 10
2.4 Clocks................................................................................................................................................................................. 14
2.5
On Board Displays (2x20 LCD & 128x64 OLED)................................................................................................................ 14
2.6 VGA
(DB15
& Video DAC).................................................................................................................................................. 17
2.7 Audio
Codec ....................................................................................................................................................................... 19
2.8 PS2
Keyboard
& Mouse Ports ............................................................................................................................................ 20
2.9
Dip & Push-Button Switches............................................................................................................................................... 20
2.10
LEDs .............................................................................................................................................................................. 21
2.11 Piezo Buzzer .................................................................................................................................................................. 21
2.12 High-speed
Serial Communication ................................................................................................................................. 21
2.13 Memory .......................................................................................................................................................................... 23
2.14 Communication
(RS232, 10/100 Ethernet, USB2.0) ...................................................................................................... 24
2.15 I/O
Connectors ............................................................................................................................................................... 28
2.16 Power ............................................................................................................................................................................. 32
3.0 Software/BSP.......................................................................................................................................................................... 33
3.1 What
is included ................................................................................................................................................................. 33
3.2 Hello
World ......................................................................................................................................................................... 33
3.3
On-Chip Peripheral Bus (OPB) External Memory Project(s)............................................................................................... 33
3.4 Web
Server......................................................................................................................................................................... 33
Figures
Figure 1 - Spartan-3 Dev (Top Side)
Figure 2 - Spartan-3 Dev (Bottom Side)......................................................................... 4
Figure 3 - Spartan-3 Development Board Picture....................................................................................................................................... 5
Figure 4 - Spartan-3 Development Board Block Diagram........................................................................................................................... 6
Figure 5 – Boundary Scan Mode Selection via JP2 ................................................................................................................................... 7
Figure 6 - Configuration / Debug Connections – Par3 ................................................................................................................................ 7
Figure 7 - Configuration / Debug Connections – Par IV ............................................................................................................................. 7
Figure 8 - JTAG Chain Standalone Mode (Default) .................................................................................................................................... 8
Figure 9 – Design Revision “BIT SEL” Jumpers JP3.................................................................................................................................. 8
Figure 10 - Fly Wire Connection J1 ............................................................................................................................................................ 9
Figure 11 - FPGA Configuration Mode Select .......................................................................................................................................... 10
Figure 12 - Design Revision Select .......................................................................................................................................................... 10
Figure 13 - I/O Voltage Selection Banks 4&5 ........................................................................................................................................... 11
Figure 14 - I/O Voltage Selection Banks 1&2 ........................................................................................................................................... 11
Figure 15 - I/O Voltage Selection Banks 2&3 ........................................................................................................................................... 11
Figure 16 - Default Jumper Placement ..................................................................................................................................................... 13
Figure 17 - Resistor Jumper Pin-out......................................................................................................................................................... 25
Figure 18 - Barrel Power Connector "J7".................................................................................................................................................. 32
