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Avnet Electronics Marketing
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Rev 1.0 04/17/2006
Released
Literature # ADS-005104
JP2
Mo
de
0
Mo
de
1
Mo
de
2
For Boundary Scan mode,
place jumpers at JP2
positions 1-2 & 5-6.
Figure 5 – Boundary Scan Mode Selection via JP2
JTAG Header (J1)
J1 is a standard 0.1” header and is intended for use with flying leads, such as those of the Xilinx Parallel Cable 3 (PC3)
downloading/debugging cable. Connect the leads as indicated below for “J1”.
Signal Name
Par-3 (J1) pin
PAR-4 Ribbon (JP6) pin
VCC 20
2
TDI 9
10
TDO 15
8
TMS 13
4
TCK 11
6
GND 19,
21
1,3,5,7,9,11 or 13
Table 3 - JTAG Headers (Par-3 & Par-4) Pin-Out
Figure 6 - Configuration / Debug Connections – Par3
Parallel Cable IV / MultiPro Ribbon (J5)
J5 is intended for connection to a 14-pin ribbon as supplied with a Xilinx Parallel Cable IV or MultiPro Desktop Tool. Connect
the ribbon cable to JP6 as shown below. Note that the ribbon and connector are keyed to ensure proper connection.
Figure 7 - Configuration / Debug Connections – Par IV
For futher information regarding Xilinx configuration solutions, please visit:
http://www.xilinx.com/products/design_resources/config_sol/index.htm
Modifying the JTAG Chain
Pin 1
Keyed Connection–
Only Plugs in One way
Lower Right Edge
of Board
LEDs
(Shown here for reference only)
J1 Header
Flying Leads –
Such as used with Parallel Cable 3