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10 of 33
Rev 1.0 04/17/2006
Released
Literature # ADS-005104
2.3 Jumper
Settings
This section provides a description of the jumper settings for the Development board. The jumpers are listed in order by JP number.
The board is ready to use out of the box with the default jumper settings.
JP1 “BNK 2&3 VRef” – Supplies a 1.25V reference voltage to the VREF inputs of banks 2 & 3. Use only if your I/O standard requires a
reference voltage of 1.25V. Note that when installed, all VREF pins in banks 2 & 3 will be connected to the 1.25V reference rail. Any
unused reference pins should be dealt with appropriately, or the FPGA may have an adverse affect on the rail. One option for unused
VREF pins is to use the config prohibit attribute in the UCF and then use tri-state option for unused I/O in bitgen. Another option may
be to use “dummy” inputs to ensure the FPGA will not drive the unused VREFs.
Default: Uninstalled; BNK 2&3 Vref not connected to 1.25V rail.
JP2 “MODE SELECT” – Configuration mode selection. Use to select the configuration mode for the FPGA. With no jumpers installed,
these pins are pulled low enabling Master Serial mode. Installing jumpers on JP2 will pull the corresponding mode pin high, as
indicated in the Figure below. See the Configuration section of this document for further information. Default: Uninstalled; Master
Serial mode; FPGA will be configured from Platform Flash.
Figure 11 - FPGA Configuration Mode Select
JP3 “Bit Select” – Design Revision Select, selects the configuration design when the PROM is programmed with multiple revisions.
When no jumpers are installed, the PROM is set for external selection mode with revision 0 selected. Installing jumpers on JP3 will pull
the corresponding select pin high, as indicated in the Figure below.
Default: Uninstalled; external enabled using Rev0
SEL0
SEL1
EN
Figure 12 - Design Revision Select
JP4 “HSWAP_EN” – Enables pull-ups on the Spartan-3 I/O pins during configuration. A pull-down resistor is used to enable the I/O pull-
ups during configuration. Install a jumper to disable the configuration pull-ups.
Default: Open; pull-ups enabled.
JP6 – JTAG chain configuration. Selects the JTAG chain configuration. Install a jumper across pins 2-3 for standalone mode. Install
jumpers across pins 1-2 and pins 4-5 to add the AvBus connector labeled “P1” to the standalone chain. These settings are described in
the Hardware section of this manual (see “Modifying the JTAG Chain” in
Boundary scan
section).
Default: Installed across pins 2-3; standalone chain mode.
JP7 – JTAG TRST#, forces TRST low.
Default: Open, pulled-high.
JP8 “ETH EN” – Ethernet Enable, connects an I/O pin on the FPGA to the reset pin of the Ethernet PHY. See the “PHY_RST#” net on
the schematic. The PHY is held in reset by a pull-down resistor when a jumper is not installed. Default: Installed, FPGA drives the
PHY reset.
JP9 “USB 5V” – USB 5.0V Power, when installed allows the USB host to supply the 5.0V rail of the evaluation board over the USB
connection. This is not recommended since the evaluation board requires more current than USB specification provides for. Using the
USB port for board power may damage the USB host (the PC or laptop).
Default: Open, board power comes from J7 connector.
JP10 “USB EEPROM WC#” – Serial EEPROM write protect, install a shunt to protect programmed data.
Default: Open, read/write enabled.
