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31 of 33
Rev 1.0 04/17/2006
Released
Literature # ADS-005104
JP1: Header 25x2
Pin
FPGA
Signal
Signal
FPGA
Pin
1 A19
HDR_IO0
HDR_IO1
A22 2
3 A20
HDR_IO2
HDR_IO3
A23 4
5 D19 HDR_IO4
HDR_IO5 A21 6
7 E19
HDR_IO6
HDR_IO7
B23 8
9 B22
HDR_IO8
HDR_IO9
C23 10
11 C22 HDR_IO10
HDR_IO11 B21 12
13 C21 HDR_IO12
HDR_IO13 E21 14
15 D21
HDR_IO14
HDR_IO15
F21 16
17 E20
HDR_IO16
HDR_IO17
B20 18
19 F20
HDR_IO18
HDR_IO19
D20 20
21 F19
HDR_IO20
HDR_IO21
B19 22
23 G19 HDR_IO22
HDR_IO23 C19 24
25 W21
HDR_IO24
HDR_IO25
W20 26
27 Y21
HDR_IO26
HDR_IO27
Y20 28
29 AC22
HDR_IO28
HDR_IO29 Y22 30
31 AD22 HDR_IO30
HDR_IO31 AB22 32
33 AB23
HDR_IO32
HDR_IO33 Y23 34
35 AD23 HDR_IO34
HDR_IO35 AA23 36
37 AE24
HDR_IO36
HDR_IO37
AA24 38
39 AF24
HDR_IO38
HDR_IO39
AB25 40
41 AB26
HDR_IO40
HDR_IO41
AD25 42
43 AE22
HDR_IO42
HDR_IO43
AE23 44
45 AF22
HDR_IO44
HDR_IO45
AF23 46
47 AF14
CLK_HDR
3.3V/5.0V
-
48
49
-
Ground
Ground
-
50
Table 28 - Header "JP1" Pin-out