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Avnet Electronics Marketing
28 of 33
Rev 1.0 04/17/2006
Released
Literature # ADS-005104
2.15 I/O Connectors
The Spartan-3 Development board is an Avalon compliant motherboard that incorporates board-to-board connectors to support Avalon
expansion boards. The connection between the Spartan-3 Development board and the Avnet daughterboards is via the Avnet standard
AvBus connectors (P1, P2, J14 and J15). The connectors on the top side of the evaluation board (P1, P2) are the host connectors,
AMP part number 179031-6. The host connectors mate with AMP part number 5-179010-6. Connectors on the bottom side (J14, J15)
are AMP part number 5-179010-6. Since the Spartan-3 Dev is intended as a host, the bottom (solder side) connectors (J14, J15) are
not populated by default.
2.15.1 AvBus Connectors
The Spartan-3 FPGA is connected to two mirrored 140-pin board-to-board AvBus standard connectors. This means that each signal
connected to P1 is mirrored on the opposite side of the board by the same pin number on J14. Similarly, P2 is mirrored by J15.
AvBus “P1”
The AvBus connector labeled “P1” is directly connected to 88 I/O of the Spartan-3. These signals, labeled AV_D(0:31), AV_A(0:31),
and AV_CTL(0:23) are connected to voltage selectable banks 0 and 1 of the FPGA.
AvBus “P2”
The AvBus connector labeled “P2” is directly connected to 93 I/O of the Spartan-3. These signals, labeled GEN_IO(0:32),
LVDS_N(0:29), and LVDS_P(0:29) are connected to voltage selectable banks 2 and 3 of the FPGA. Note that the signals labeled
LVDS are routed as differential pairs. This means that, for example, LVDS_N(0) is tightly coupled with LVDS_P(0). Consequently, any
LVDS signal left floating will experience cross-talk from it’s counterpart signal. This should be taken into account by the user when
developing custom expansion cards.
AvBus “J14”
The AvBus connector labeled “J14” is a mirror of “P1”. All signals are connected, pin-to-pin with P1. The only exceptions are the JTAG
signals. This connector is not populated by default since the Spartan-3 Dev is intended to be the host.
AvBus “J15”
The AvBus connector labeled “J15” is a mirror of “P2”. All signals are connected, pin-to-pin with P2. This connector is not populated by
default since the Spartan-3 Dev is intended to be the host.
2.15.2 Header “JP1”
The 50-pin header labeled “J17” on the Spartan-3 Development board is connected to 47 I/O pins on the Spartan-3 FPGA. Pin 48 on
the header provides either 3.3V or 5.0V depending on the jumper pad installation on JT9 (3.3V is the default). Note that the pins of
header JP1 are shared with several other peripherals including Video DAC, Audio Codec, PS2, and buzzer by way of bus switches.
The bus switches may be disabled by removing JP20. Doing so will isolate the header from the extra peripherals, leaving only the
header connected directly to the FPGA.
The tables on the following pages show pin-outs for the header and AvBus connectors.
