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Rev 1.0 04/17/2006
Released
Literature # ADS-005104
2.13 Memory
The Spartan-3 Development board is populated with 32MB DDR SDRAM, 16MB Flash, and 2MB SRAM. Additional memory including
Flash, SDRAM, and SRAM are available with the purchase of the Avnet Communications/Memory Module.
2.13.1 DDR
SDRAM
Manufacturer: Micron
Part #: MT46V16M16
One Micron DDR SDRAM device, part number: MT46V16M16-4, provides a 16-bit data bus.
Attributes of the DDR SDRAM on the Spartan-3 Development board:
32MB (one 16 Meg x 16 device)
60-ball FBGA (16mm x 9mm)
Board supplies 2.5V to VDD and VDDQ
6ns access time (CL = 2 @ 133 MHz, CL = 2.5 @ 333 MHz)
The following table lists the timing parameters required to set up the SDRAM peripheral in EDK for 100 MHz operation (parameters are
entered in the MHS file). If a timing parameter is left out of the peripheral instantiation, a default value is automatically used. The
Software/BSP section of this manual has more information about setting up peripherals in EDK.
PLB DDRperipheral – Timing Parameter
Time (ps) or
Number
C_DDR_TMRD 12000
C_DDR_TWR 15000
C_DDR_TWTR 1
C_DDR_TRAS 70000
C_DDR_TRC 60000
C_DDR_TRFC 72000
C_DDR_TRCD 18000
C_DDR_TRRD 12000
C_DDR_TRP 18000
C_DDR_TREFI 7800000
C_DDR_CAS_LAT 2
C_DDR_DWIDTH 32
C_DDR_AWIDTH 13
C_DDR_COL_AWIDTH 9
C_DDR_BANK_AWIDTH 2
C_PLB_CLK_PERIOD_PS 10000
Table 19 - Timing Parameters for DDR SDRAM Peripheral
2.13.2 Flash
Manufacturer: Intel
Part #: TE28F640J3C120
Two 64 Mbit devices, 4M x 16, make up the 32-bit Flash data bus. The devices have an operating voltage of 3.3V and provide 16 MB
total of Flash memory. The Flash is connected to the Spartan-3 FPGA via a shared memory bus which also services the SRAM and
one AvBus connector (P3).
An example project, using the OPB_EMC is included with the Spartan-3 Dev kit. This example will provide correct timing parameters
for operating the SRAM and Flash devices. See the Software/BSP section of this manual for more information.
