ADT7476
Rev. B | Page 68 of 72
Table 50. Register 0x74—Interrupt Mask Register 1 (Power-On Default = 0x00)
Bit
Name
R/W
Description
[0]
2.5 V/ THERM
R/W
2.5 V/ THERM = 1, masks SMBALERT for out-of-limit conditions on the 2.5 V/ THERM
timer
channel.
[1] V
CCP
R/W
V
CCP
= 1, masks SMBALERT for out-of-limit conditions on the V
CCP
channel.
[2] V
CC
R/W
V
CC
= 1, masks SMBALERT for out-of-limit conditions on the V
CC
channel.
[3] 5V
R/W 5 V = 1, masks SMBALERT for out-of-limit conditions on the 5 V channel.
[4] R1T
R/W R1T = 1, masks SMBALERT for out-of-limit conditions on the Remote 1 temperature channel.
[5] LT
R/W LT = 1, masks SMBALERT for out-of-limit conditions on the local temperature channel.
[6] R2T
R/W R2T = 1, masks SMBALERT for out-of-limit conditions on the Remote 2 temperature channel.
[7] OOL
R/W OOL = 1, masks SMBALERT for any out-of-limit condition in Interrupt Status Register 2.
Table 51. Register 0x75—Interrupt Mask Register 2 (Power-On Default = 0x00)
Bit
Name
R/W
Description
[0] 12
V/VC R/W When Pin 21 is configured as a 12 V input, 12 V/VC = 1 masks SMBALERT for out-of-limit conditions on
the 12 V channel. When Pin 21 is programmed as VID5, this bit masks an SMBALERT if the VID5 VID code
bit changes.
[1]
OVT
R/W
OVT = 1, masks SMBALERT for overtemperature THERM conditions.
[2]
FAN1
R/W
FAN1 = 1, masks SMBALERT for a Fan 1 fault.
[3]
FAN2
R/W
FAN2 = 1, masks SMBALERT for a Fan 2 fault.
[4]
FAN3
R/W
FAN3 = 1, masks SMBALERT for a Fan 3 fault.
[5]
F4P
R/W
If Pin 14 is configured as TACH 4, F4P = 1 masks SMBALERT for a Fan 4 fault.
If Pin 14 is configured as THERM, F4P = 1 masks SMBALERT for an exceeded THERM timer limit.
If Pin 14 is configured as GPIO6, F4P = 1 masks SMBALERT when GPIO6 is an input and GPIO6 is
asserted.
[6]
D1
R/W
D1 = 1 masks SMBALERT for a diode open or short on a Remote 1 channel.
[7] D2
R/W D2 = 1 masks SMBALERT for a diode open or short on a Remote 2 channel.
Table 52. Register 0x76—Extended Resolution Register 1
(Power-On Default = 0x00)
Bit
Name
R/W
Description
[1:0]
2.5 V
Read-only
2.5 V
LSBs. Holds the 2 LSBs of the 10-bit 2.5 V measurement.
[3:2]
V
CCP
Read-only
V
CCP
LSBs. Holds the 2 LSBs of the 10-bit V
CCP
measurement.
[5:4] V
CC
Read-only
V
CC
LSBs. Holds the 2 LSBs of the 10-bit V
CC
measurement.
[7:6]
5 V
Read-only
5 V LSBs. Holds the 2 LSBs of the 10-bit 5 V measurement.
1
If this register is read, this register and the registers holding the MSB of each reading are frozen until read.
Table 53. Register 0x77—Extended Resolution Register 2
(Power-On Default = 0x00)
Bit
Name
R/W
Description
[1:0]
12 V
Read-only
12 V
LSBs. Holds the 2 LSBs of the 10-bit 12 V measurement.
[3:2]
TDM1
Read-only
Remote 1 Temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 1 temperature measurement.
[5:4]
LTMP
Read-only
Local Temperature LSBs. Holds the 2 LSBs of the 10-bit local temperature measurement.
[7:6]
TDM2
Read-only
Remote 2 Temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 2 temperature measurement.
1
If this register is read, this register and the registers holding the MSB of each reading are frozen until read.
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