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ADT7476

 

Rev. B | Page 15 of 72 

R/W

0

SCL

SDA

1

0

1

1

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

ACK. BY

ADT7476

STOP BY

MASTER

START BY

MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

ADDRESS POINTER REGISTER BYTE

1

1

9

ACK. BY

ADT7476

9

05382-020

 

Figure 19. Writing to the Address Pointer Register Only 

 

R/W

0

SCL

SDA

1

0

1

1

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

NO ACK. BY

MASTER

STOP BY

MASTER

START BY

MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

DATA BYTE FROM ADT7476

1

1

9

ACK. BY

ADT7476

9

05382-021

 

Figure 20. Reading Data from a Previously Selected Register

It is possible to read a data byte from a data register without 
first writing to the address pointer register if the address pointer 
register is already at the correct value. However, it is not possible 
to write data to a register without writing to the address pointer 
register because the first data byte of a write is always written to 
the address pointer register. 

In addition to supporting the send byte and receive byte 
protocols, the ADT7476 also supports the read byte protocol. 
(See 

System Management Bus (SMBus) Specifications Version 2 

for more information; it is available

 at www.smbus.org/specs.

If several read operations or write operations must be performed 
in succession, the master can send a repeat start condition 
instead of a stop condition to begin a new operation. 

WRITE OPERATIONS 

The SMBus specification defines several protocols for different 
types of read and write operations. The ones used in the ADT7476 
are discussed in this section and the next section. The following 
abbreviations are used in the diagrams: 

S – Start 
P – Stop 
R – Read 
W – Write 
A – Acknowledge 
A – No acknowledge 

The ADT7476 uses the following SMBus write protocols. 

Send Byte  

In this operation, the master device sends a single command 
byte to a slave device, as follows: 

1.

 

The master device asserts a start condition on SDA. 

2.

 

The master sends the 7-bit slave address followed by 
the write bit (active low). 

3.

 

The addressed slave device asserts ACK on SDA.  

4.

 

The master sends a command code. 

5.

 

The slave asserts ACK on SDA. 

6.

 

The master asserts a stop condition on SDA, and the 
transaction ends. 

For the ADT7476, the send byte protocol is used to write a 
register address to RAM for a subsequent single-byte read from 
the same address. This operation is illustrated in Figure 21

05382-022

SLAVE

ADDRESS

W A

S

A P

REGISTER

ADDRESS

2

3

1

5

6

4

 

Figure 21. Setting a Register Address for Subsequent Read 

If the master is required to read data from the register immedi-
ately after setting up the address, it can assert a repeat start 
condition immediately after the final ACK and carry out a 
single-byte read without asserting an intermediate stop 
condition. 

www.BDTIC.com/ADI

Содержание dBCool ADT7476

Страница 1: ...dBCool controller is a thermal monitor and multiple PWM fan controller for noise sensitive or power sensitive applications requiring active system cooling The ADT7476 can drive a fan using either a l...

Страница 2: ...ode Change Detect Function 20 Programming the GPIOs 20 Temperature Measurement Method 20 Factors Affecting Diode Accuracy 22 Additional ADC Functions for Temperature Measurement 23 Limits Status Regis...

Страница 3: ...59 Changes to Bit 1 in Table 51 68 3 06 Rev 0 to Rev A Changes to Features Section 1 Changes to Table 1 4 Inserted Table 3 6 Changes to Feature Comparisons Between ADT7476 and ADT7468 Section 11 Chan...

Страница 4: ...version Time Local Temperature 12 ms Averaging enabled Conversion Time Remote Temperature 38 ms Averaging enabled Total Monitoring Cycle Time 145 ms Averaging enabled 19 ms Averaging disabled Input Re...

Страница 5: ...A Rise Time tr 1000 ns SCL SDA Fall Time tf 300 s Data Setup Time tSU DAT 250 ns Detect Clock Low Timeout tTIMEOUT 15 35 ms Can be disabled 1 All voltages are measured with respect to GND unless other...

Страница 6: ...ature 260 C Lead Temperature Soldering 10 sec 300 C ESD Rating 1500 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only f...

Страница 7: ...tachometer input to measure speed of Fan 3 10 PWM2 Digital Output Open Drain Requires 10 k typical pull up Pulse width modulated output to control Fan 2 speed Can be configured as a high or low freque...

Страница 8: ...x43 22 2 5VIN Analog Input Monitors 2 5 V supply typically a chipset voltage THERM Alternatively this pin can be reconfigured as a bidirectional omnidirectional THERM pin Can be used to time and monit...

Страница 9: ...REQUENCY Hz TEMPERATURE ERROR C 100mV 60mV 40mV 05382 007 Figure 6 Remote Temperature Error vs Common Mode Noise Frequency 70 60 50 40 30 20 0 10 0 100M 200M 300M 400M 500M 600M NOISE FREQUENCY Hz TEM...

Страница 10: ...pply Noise Frequency 3 0 2 5 2 0 1 5 1 0 0 5 0 0 5 40 20 0 20 40 60 85 OIL BATH TEMPERATURE C TEMPERATURE ERROR C 1 0 1 5 105 125 05382 012 Figure 11 Internal Temperature Error vs Temperature 3 0 2 5...

Страница 11: ...Operating Point Register 0x33 Register 0x34 and Register 0x35 Previously TRANGE defined the slope of the automatic fan control algorithm For the ADT7476 TRANGE now defines a true temperature range Fo...

Страница 12: ...nnel Remote temperature zone measured through Remote 2 temperature channel Local temperature zone measured through the internal temperature channel Bidirectional THERM pin This feature allows Intel Pe...

Страница 13: ...T IF THE ADT7476 IS PLACED INTO ADDR SELECT MODE PINS 13 AND 14 CANNOT BE USED AS THE ALTERNATIVE FUNCTIONS PWM3 TACH4 THERM UNLESS THE CORRECT CIRCUIT IS MUXED IN AT THE CORRECT TIME OR DESIGNED TO H...

Страница 14: ...ut using the SMBus The ADT7476 is connected to this bus as a slave device under the control of a master controller which is usually but not necessarily the ICH The ADT7476 has three 7 bit serial bus a...

Страница 15: ...nd a repeat start condition instead of a stop condition to begin a new operation WRITE OPERATIONS The SMBus specification defines several protocols for different types of read and write operations The...

Страница 16: ...identify itself to the host when multiple devices exist on the same bus The SMBALERT output can be used as either an interrupt out put or an SMBALERT One or more outputs can be connected to a common...

Страница 17: ...annel is a high and low limit register Exceeding the programmed high or low limit causes the appropriate status bit to be set Exceeding either limit can also generate SMBALERT interrupts Register 0x44...

Страница 18: ...uration Register 2 0x73 Bit 4 1 averaging off Bit 5 1 bypass input attenuators Bit 6 1 single channel convert mode TACH1 Minimum High Byte Register 0x55 Bits 7 5 select ADC channel for single channel...

Страница 19: ...0156 3 3300 to 3 3415 2 2000 to 2 2042 1 6650 to 1 6682 1 5000 to 1 5029 512 scale 10000000 00 12 0000 to 12 0156 5 0025 to 5 0090 3 3000 to 3 3042 2 4975 to 2 5007 2 2500 to 2 2529 768 scale 11000000...

Страница 20: ...d reported back by the ADT7476 Bit 0 of Interrupt Status Register 2 0x42 is the 12 V VC bit and denotes a VID change when set The VID code change bit is set when the logic states on the VID inputs are...

Страница 21: ...ter to remove noise and to a chopper stabilized amplifier that performs the functions of amplification and rectification of the waveform to produce a dc voltage proportional to VBE This voltage is mea...

Страница 22: ...the best accuracy is obtained by choosing devices according to the following criteria Base emitter voltage greater than 0 25 V at 11 A at the highest operating temperature Base emitter voltage less t...

Страница 23: ...that SMBALERT is set as an output on the appropriate pin Register 0x4E Remote 1 Temperature Low Limit 0x81 default Register 0x4F Remote 1 Temperature High Limit 0x7F default Register 0x50 Local Tempe...

Страница 24: ...ure 111 Remote 2 temperature FANS TEMPERATURE 100 HYSTERESIS C THERM LIMIT 05382 029 Configuration Register 2 0x73 Figure 28 THERM Temperature Limit Operation Bit 4 1 averaging off THERM can be disabl...

Страница 25: ...mally the only conditions of interest only high limits exist for fan TACHs Because the fan TACH period is actually being measured exceeding the limit indicates a slow or stalled fan Fan Limit Register...

Страница 26: ...gone away until read The only way to clear the status bit is to read the status register after the event has gone Interrupt mask registers Register 0x74 and Register 0x75 allow individual interrupt s...

Страница 27: ...g Interrupt Sources Interrupt Mask Register 1 and Interrupt Mask Register 2 are located at Register 0x74 and Register 0x75 These allow individ ual interrupt sources to be masked out to prevent SMBALER...

Страница 28: ...ister 3 0x78 to 1 This works only if the fan is already running for example in manual mode when the current duty cycle is above Register 0x00 or in automatic mode when the temperature is above TMIN If...

Страница 29: ...imer Note that depending on which pins are configured as a THERM timer setting the F4P bit Bit 5 of Interrupt Mask Register 2 0x75 or Bit 0 of Interrupt Mask Register 1 0x74 masks out SMBALERT althoug...

Страница 30: ...nificantly because THERM is asserting more frequently on an hourly basis Alternatively OS or BIOS level software can timestamp when the system is powered on If an SMBALERT is gen erated due to the THE...

Страница 31: ...pull up an FET with large input capacitance can cause the PWM output to become distorted and adversely affect the fan control range This is a requirement only when using high frequency PWM mode Typica...

Страница 32: ...Figure 38 and Figure 39 The SYNC bit in Register 0x62 enables this function Figure 37 Driving a 4 Wire Fan Driving Two Fans from PWM3 The ADT7476 has four TACH inputs available for fan speed measurem...

Страница 33: ...ge should be chosen so that it is greater than VIH of the TACH input but less than 3 6 V allowing for the voltage tolerance of the Zener A value of between 3 V and 3 6 V is suitable 05382 043 12V VCC...

Страница 34: ...the device is essentially measuring the fan TACH period the higher the count value the slower the fan is actually running A 16 bit fan tachometer reading of 0xFFFF indicates that the fan has stalled...

Страница 35: ...fferent spin up characteristics and take different times to overcome inertia The ADT7476 runs the fans just fast enough to overcome inertia and is quieter on spin up than fans programmed to spin up fo...

Страница 36: ...Bits 7 5 BHVR 111 manual mode Once under manual control each PWM output can be manu ally updated by writing Register 0x30 to Register 0x32 PWMx current duty cycle registers Programming the PWM Curren...

Страница 37: ...temperature channels that can be connected to a CPU on chip thermal diode available on Intel Pentium class CPUs and other CPUs These three temperature channels can be used as the basis for automatic...

Страница 38: ...ADT7476 functionality is used PWM2 or SMBALERT TACH4 fan speed measurement or overtemperature THERM function 2 5 V voltage monitoring or overtemperature THERM function 12 V voltage monitoring or VID5...

Страница 39: ...lowing features Six VID inputs VID0 to VID5 for VRM10 support Two PWM outputs for fan control of up to three fans The front and rear chassis fans are connected in parallel Three TACH fan speed measure...

Страница 40: ...ally controlled Three TACH fan speed measurement inputs VCC measured internally through Pin 4 CPU core voltage measurement VCORE 2 5 V measurement input used to monitor CPU current connected to VCOMP...

Страница 41: ...and PWM3 outputs The values selected for these bits determine how the mux connects a temperature measurement channel to a PWM output Automatic Fan Control Mux Options Bits 7 5 BHVR Register 0x5C Regi...

Страница 42: ...control three fans The CPU fan sink is controlled by PWM1 the front chassis fan is controlled by PWM2 and the rear chassis fan is controlled by PWM3 The mux is configured for the following fan contro...

Страница 43: ...h each temperature measurement channel Remote 1 local and Remote 2 temperature Once the TMIN value is exceeded the fan turns on and runs at the minimum PWM duty cycle The fan turns off once the temper...

Страница 44: ...system acoustic benefit PWMMIN should be as low as possible Depending on the fan used the PWMMIN set ting is usually in the 20 to 33 duty cycle range This value can be found through fan validation TEM...

Страница 45: ...5 PWMMAX FOR PWM FAN OUTPUTS PWMMAX is the maximum duty cycle at which each fan in the system runs under the automatic fan speed control loop For maximum system acoustic benefit PWMMAX should be as l...

Страница 46: ...ning at 50 PWM duty cycle 3 Determine the slope of the required control loop to meet these requirements 4 Using the ADT7476 evaluation software graphically program and visualize this functionality Ask...

Страница 47: ...Register 0x63 changes how fast the fan speed increases decreases in the event of a temperature spike The PWM duty cycle increases until the PWM duty cycle reaches the appropriate duty cycle as define...

Страница 48: ...0 The rear chassis fan is configured to run at PWMMIN 30 The CPU fan is configured to run at PWMMIN 10 Note that the control range for 4 wire fans is much wider than for 3 wire fans In many cases 4 wi...

Страница 49: ...Registers Register 0x6D Remote 1 and Local Temperature Hysteresis Register Bits 7 4 Remote 1 Temperature Hysteresis 4 C default Bits 3 0 Local Temperature Hysteresis 4 C default Register 0x6E Remote 2...

Страница 50: ...ion In some applications it is required that fans not turn off below TMIN but remain running at PWMMIN Bits 7 5 of Enhanced Acoustics Register 1 0x62 allow the fans to be turned off or to be kept spin...

Страница 51: ...s the ramp rate for PWM outputs associated with the local temperature channel 000 37 5 sec 001 18 8 sec 010 12 5 seconds 011 7 5 seconds 100 4 7 seconds 101 3 1 seconds 110 1 6 seconds 111 0 8 seconds...

Страница 52: ...In computers that support S3 and S5 states the core voltage of the processor is lowered in these states When monitoring THERM the THERM timer should be disabled during these states When the VCCP volta...

Страница 53: ...te 7 6 5 4 3 2 1 0 0x00 0x29 R TACH1 High Byte 15 14 13 12 11 10 9 8 0x00 0x2A R TACH2 Low Byte 7 6 5 4 3 2 1 0 0x00 0x2B R TACH2 High Byte 15 14 13 12 11 10 9 8 0x00 0x2C R TACH3 Low Byte 7 6 5 4 3 2...

Страница 54: ...imit 7 6 5 4 3 2 1 0 0x81 0x53 R W Remote 2 Temp High Limit 7 6 5 4 3 2 1 0 0x7F 0x54 R W TACH1 Mini mum Low Byte 7 6 5 4 3 2 1 0 0xFF 0x55 R W TACH1 Mini mum High Byte 15 14 13 12 11 10 9 8 0xFF 0x56...

Страница 55: ...le RES RES RES RES RES RES RES XEN 0x00 Yes 0x70 R W Remote 1 Temperature Offset 7 6 5 4 3 2 1 0 0x00 Yes 0x71 R W Local Temperature Offset 7 6 5 4 3 2 1 0 0x00 Yes 0x72 R W Remote 2 Temperature Offse...

Страница 56: ...urn to their programmed state after a spin up cycle 7 ExtraSlow R W When this bit is set all fan smoothing times are increased by an additional 39 2 1 A THERM event always overrides any fan setting ev...

Страница 57: ...bytes are read the low byte must be read first Both the low and high bytes are then frozen until read At power on these registers contain 0x0000 until such time as the first valid fan TACH measurement...

Страница 58: ...mal protection Table 27 Register 0x41 Interrupt Status Register 1 Power On Default 0x00 Bit Name R W Description 0 2 5 V THERM Read only 2 5 V 1 indicates that the 2 5 V high or low limit has been exc...

Страница 59: ...indicates that Fan 4 has dropped below minimum speed or has stalled This bit is not set when the PWM3 output is off THERM Read only If Pin 14 is configured as the THERM timer input for THERM monitorin...

Страница 60: ...imit 0x81 0x53 R W Remote 2 temperature high limit 0x7F 1 Exceeding any of these temperature limits by 1 C causes the appropriate status bit to be set in the interrupt status register Setting the Conf...

Страница 61: ...two valid TACH rising edges are seen from the fan If there is not a valid TACH signal during the fan TACH measurement directly after the fan start up timeout period then the TACH measurement reads 0xF...

Страница 62: ...egisters Power On Default 0xC4 Bit Name R W Description 2 0 FREQ R W These bits control the PWMx frequency only apply when PWM channel is in low frequency mode 000 11 0 Hz 001 14 7 Hz 010 22 1 Hz 011...

Страница 63: ...three fans to be driven from PWM3 output and their speeds to be measured SYNC 0 synchronizes only TACH3 and TACH4 to PWM3 output 5 MIN1 R W When the ADT7476 is in automatic fan control mode this bit...

Страница 64: ...3 R W When this bit is 1 smoothing is enabled on the local temperature channel 6 4 ACOU2 R W Assuming that PWMx is associated with the Remote 2 temperature channel these bits define the maximum rate o...

Страница 65: ...ty cycle for PWMx 0x00 0 duty cycle fan off 0x40 25 duty cycle 0x80 50 duty cycle 0xFF 100 duty cycle fan full speed 1 These registers become read only when the ADT7476 is in automatic fan control mod...

Страница 66: ...o a particular temperature channel Once the temperature for that channel falls below its TMIN value the fan remains running at PWMMIN duty cycle until the temperature TMIN hysteresis Up to 15 C of hys...

Страница 67: ...TACH channel 1 Fan1Detect Read Fan1Detect 1 indicates that a 4 wire fan is connected to the TACH1 input 2 Fan2Detect Read Fan2Detect 1 indicates that a 4 wire fan is connected to the TACH2 input 3 Fan...

Страница 68: ...ult 5 F4P R W If Pin 14 is configured as TACH 4 F4P 1 masks SMBALERT for a Fan 4 fault If Pin 14 is configured as THERM F4P 1 masks SMBALERT for an exceeded THERM timer limit If Pin 14 is configured a...

Страница 69: ...DC2 R W DC2 1 enables TACH measurements to be continuously made on TACH2 Fans must be driven by dc Setting this bit prevents pulse stretching because it is not required for dc driven motors 6 DC3 R W...

Страница 70: ...0 changes the temperature range to the Offset 64 temperature range When this bit is changed the ADT7476 interprets all relevant temperature register values as defined by this bit 1 Temp Offset R W Tem...

Страница 71: ...be disabled on any channel by In Offset 64 mode writing 64 C to the appropriate THERM temperature limit In twos complement mode writing 128 C to the appropriate THERM temperature limit 3 Max Speed on...

Страница 72: ...l Outline Package QSOP RQ 24 Dimensions shown in inches ORDERING GUIDE Model Termperature Range Package Description Package Option ADT7476ARQZ1 40 C to 125 C 24 Lead QSOP RQ 24 ADT7476ARQZ REEL1 40 C...

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