Analog Devices dBCool ADT7476, Руководство пользователя

Страница: 57 / 72

ADT7476
Rev. B | Page 57 of 72
Table 22. Temperature Reading Registers (Power-On Default = 0x80)
1 , 2 , 3
Register Address R/W Description
0x25 Read-only Remote 1 temperature reading (8 MSBs of reading).
4
0x26 Read-only Local temperature reading (8 MSBs of reading).
0x27 Read-only Remote 2 temperature reading (8 MSBs of reading).
4
1 If the extended resolution bits of these readings are also being read, the extended resolution registers (0x76, 0x77) must be read first. Once the extended resolution
registers have been read, all associated MSB reading registers are frozen until read. Both the extended resolution registers and MSB registers are frozen.
2
These temperature readings can be in twos complement or Offset 64 format; this interpretation is determined by Bit 0 of Configuration Register 5 (0x7C).
3
In twos complement mode, a temperature reading of −128°C (0x80) indicates a diode fault (open or short) on that channel.
4 In Offset 64 mode, a temperature reading of −64°C (0x00) indicates a diode fault (open or short) on that channel.
Table 23. Fan Tachometer Reading Registers (Power-On Default = 0x00)
1
Register Address R/W Description
0x28 Read-only TACH1 low byte.
0x29 Read-only TACH1 high byte.
0x2A Read-only TACH2 low byte.
0x2B Read-only TACH2 high byte.
0x2C Read-only TACH3 low byte.
0x2D Read-only TACH3 high byte.
0x2E Read-only TACH4 low byte.
0x2F Read-only TACH4 high byte.
1 These registers count the number of 11.11 μs periods (based on an internal 90 kHz clock) that occur between a number of consecutive fan TACH pulses (default = 2).
The number of TACH pulses used to count can be changed using the fan pulses per revolution register (0x7B). This allows the fan speed to be accurately measured.
Because a valid fan tachometer reading requires that two bytes are read, the low byte must be read first. Both the low and high bytes are then frozen until read. At
power-on, these registers contain 0x0000 until such time as the first valid fan TACH measurement is read into these registers. This prevents false interrupts from
occurring while the fans are spinning up. A count of 0xFFFF indicates that a fan is one of the following:
•
Stalled or blocked (object jamming the fan).
•
Failed (internal circuitry destroyed).
•
Not populated. (The ADT7476 expects to see a fan connected to each TACH. If a fan is not connected to that TACH, its TACH minimum high and low bytes should
be set to 0xFFFF.)
•
Alternate function, for example, TACH4 reconfigured as THERM pin.
Table 24. PWM Current Duty Cycle Registers (Power-On Default = 0xFF)
1
Register Address R/W Description
0x30 R/W PWM1 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).
0x31 R/W PWM2 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).
0x32 R/W PWM3 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).
1 These registers reflect the PWM duty cycle driving each fan at any given time. When in automatic fan speed control mode, the ADT7476 reports the PWM duty cycles
back through these registers. The PWM duty cycle values vary according to temperature in automatic fan speed control mode. During fan startup, these registers
report back 0x00. In manual mode, the PWM duty cycle outputs can be set to any duty cycle value by writing to these registers.
Table 25. PWM Maximum Duty Cycle (Power-On Default = 0xFF)
1 , 2
Register Address R/W 2 Description
0x38 R/W Maximum duty cycle for PWM1 output, default = 100% (0xFF.)
0x39 R/W Maximum duty cycle for PWM2 output, default = 100% (0xFF).
0x3A R/W Maximum duty cycle for PWM3 output, default = 100% (0xFF).
1
These registers set the maximum PWM duty cycle of the PWM output.
2 This register becomes read-only when the Configuration Register 1 LOCK bit is set to 1. Any subsequent attempts to write to this register fail.
www.BDTIC.com/ADI